Abstract: The present invention makes it possible to transfer information between processors by a method that places little burden on the reception side processors. The information processing device is a device that processes information using a plurality of processors, comprising one or more first processors that have one or a plurality of local memories, and one or more second processors that write write information directly into the local memory that the target first processor has. The second processors store address maps in which local memory addresses for the first processors are recorded; these second processors acquire local memory addresses from these address maps, and write write information into the acquired local memory addresses.

Abstract: A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.

Abstract: A system for managing variable sized pages of possibly non contiguous blocks in a Non-Volatile-Storage (NVS) for attaining a consistent NVS that survives malfunction events. Each page includes a self describing block or linked list of self describing blocks. the system includes: Volatile Storage storing auxiliary modules, means for performing an atomic “create a new page” procedure. Means for performing an atomic write “add block” procedure for adding a possibly non contiguous block to a page. The newly added block has a back pointer to a previous block in the page. Means for performing a “delete page” procedure for deleting all blocks in a page. Means for performing a recovery procedure for rolling backward the add block procedure and rolling forward the delete page procedure, in case of malfunction event, thereby attaining consistent NVS.

Abstract: A data storage apparatus includes a flash memory and a control unit that controls the rewriting of data in the flash memory. The flash memory is divided into sectors, each of which is completely erasable in a time T. During a rewriting operation, multiple sectors are erased simultaneously for a time U less than T, and new data are written in a sector that has undergone multiple erasures and is now fully erased. The new data typically replace data stored in a sector that proceeds to be erased during multiple rewriting operations. The duration of each rewriting operation is reduced because the erasing process lasts for time U instead of time T.

Abstract: A memory has a set of address spaces to which token data is written and read. Each address space has a token status bit. A token generator allocates token data to the memory address spaces. Upon a reset occurring, a logic circuit provides logic “0” to the token generator disabling status bit checking control so that all the tokens can be issued sequentially. New token data is allocated to the address spaces sequentially and the respective status bit is updated or maintained as logic “1”. When all address spaces have been allocated, the logic circuit provides the actual state of the status bit to the token generator to control subsequent allocations.

Abstract: In order to manage the various types of attribute information within the storage-device system, the storage-device system includes the following databases within a file-access controlling memory: a database for managing index information for managing contents of the files, and an index retrieval program, a database for managing the attribute information on the files, and a database for managing storage positions of blocks configuring a file. When the storage-device system receives an access request to a file, the utilization of these databases allows the storage-device system to make the access to the access-target file.

Abstract: A method for calculating a block cache size for a host process or application on a computer based at least upon virtual memory page evictions and/or virtual memory page reclamations for the computer. A virtual memory page eviction is the act of removing the contents of a physical memory page for the purpose of loading it with the contents of another virtual memory page. A virtual memory page reclamation is the return of a page to a working set that was previously removed by the operating system due to memory constraints. The page must not have been evicted. Additional fundamental properties of the application and the computer may be used, such as available physical memory on the computer, total physical memory, and block evictions. A block eviction is the act of removing the contents of a block from the block cache for the purpose of loading it with new contents.

Abstract: An efficient memory management method for handling large data volumes, comprising a memory management interface between a plurality of applications and a physical memory, determining a priority list of buffers accessed by the plurality of applications, providing efficient disk paging based on the priority list, ensuring sufficient physical memory is available, sharing managed data buffers among a plurality of applications, mapping and unmapping data buffers in virtual memory efficiently to overcome the limits of virtual address space.

Abstract: An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters which correspond to respective contiguous region portions and which are located at two opposite ends of the first series of address counters. The path switches are provided at connection paths between the second and the third series of address counters. The path switches disconnect the first series of address counters and directly connect the second and third series of address counters or disconnect the direct connection between the second and third series of address counters and connect the first series of address counters to and between the second and the third series of address counters. The control circuit control the path switches.