Patents Examined by Leslie P. Cruz
-
Patent number: 10192892Abstract: A device includes a backplane having multiple output terminals arranged in an array on an output surface of the backplane. The device further includes an active matrix array comprising thin film solid state optical switches coupled respectively between an input terminal of the backplane and the output terminals. Storage capacitors may be coupled respectively to the output terminals. A pixelated light source provides pixelated light that controls the optical switches.Type: GrantFiled: May 29, 2015Date of Patent: January 29, 2019Assignee: Palo Alto Research Center IncorporatedInventors: JengPing Lu, David K. Biegelsen, Patrick Yasuo Maeda
-
Patent number: 9646929Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.Type: GrantFiled: June 13, 2013Date of Patent: May 9, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Hsueh-Chung Chen, Chiahsun Tseng, Chun-Chen Yeh, Ailian Zhao
-
Patent number: 7541617Abstract: In a radiation image pickup device including: a sensor element for converting radiation into an electrical signal; and a thin film transistor connected to the sensor element, an electrode of the sensor element connected to the thin film transistor is disposed above the thin film transistor, and that the thin film transistor has a top gate type structure in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are laminated in this order on a substrate, so that a channel portion of the thin film transistor is protected by a gate electrode, thereby providing stable TFT characteristics without undesirable turning ON any of the TFT elements due to the back gate effect by the fluctuation in electric potentials corresponding to outputs from the sensor electrodes, and thereby greatly improving image quality.Type: GrantFiled: February 10, 2004Date of Patent: June 2, 2009Assignee: Canon Kabushiki KaishaInventors: Chiori Mochizuki, Masakazu Morishita, Minoru Watanabe, Takamasa Ishii, Keiichi Nomura
-
Patent number: 7166908Abstract: An optical device according to the present invention includes a device substrate, a translucent member, an optical element chip and a conductive portion. On a surface of the device substrate, an opening is provided so as to extend substantially in the vertical direction with respect to a surface of the device substrate and pass through the device substrate, the translucent member is provided so as to cover a first opening mouth of the opening, and the optical element chip is provided so as to cover the other opening mouth thereof. Part of the conductive portion is buried in the device substrate. The outline of the first opening mouth has a point-asymmetrical shape with respect to an approximate center point of the first opening mouth.Type: GrantFiled: October 6, 2005Date of Patent: January 23, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Eizou Fujii, Toshiyuki Fukuda
-
Patent number: 7141882Abstract: A method of manufacturing a semiconductor wafer device, including the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.Type: GrantFiled: July 7, 2005Date of Patent: November 28, 2006Assignee: Fujitsu LimitedInventor: Kenichi Watanabe