Patents Examined by Lindsay Wickers
  • Patent number: 7772109
    Abstract: A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion of a structural body 120 corresponding to a third region C1 is folded so as to oppose a second structural body 22 to a second structural body 62 and the first multilayer wiring structural body 16 is electrically connected to the second multilayer wiring structural body 56.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: August 10, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yoshihiro Machida
  • Patent number: 7763520
    Abstract: A capacitor device includes a substrate, a first conductive structure, a second conductive structure, a dielectric layer structure, and a recess in the substrate. The first and second conductive structures are disposed on opposite sides of the dielectric layer structure, and the dielectric layer structure extends in a meander-shaped manner in a cross-section through the recess.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: July 27, 2010
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Raimund Foerg, Klaus Koller, Kai-Olaf Subke
  • Patent number: 7745871
    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: June 29, 2010
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Yong-Kyu Lee
  • Patent number: 7745245
    Abstract: At least one recess and/or protruding portion is created on the surface portion of a substrate for scattering or diffracting light generated in a light emitting region. The recess and/or protruding portion has a shape that prevents crystal defects from occurring in semiconductor layers.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: June 29, 2010
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 7696054
    Abstract: A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung-Soo Kim
  • Patent number: 7682863
    Abstract: A Complementary Metal Oxide Semiconductor (CMOS) image sensor includes a red photodiode formed in an first epitaxial layer, an isolation layer formed with a contact region left in a partial area of the red photodiode, a green photodiode formed in a surface of the isolation layer, a contact formed in the contact region at a predetermined spatial distance from the green photodiode, a second epitaxial layer formed on the first epitaxial layer in which the green photodiode is formed, a plurality of plugs formed in the second epitaxial layer and electrically connected to the green photodiode and the contact, a device isolation film formed in a surface of the second epitaxial layer, a blue photodiode formed in a surface of the second epitaxial layer above the green photodiode, and a well region formed in the second epitaxial layer inside the plug.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 23, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hyuk Woo
  • Patent number: 7678596
    Abstract: First and second semiconductor lasers interelement-separated from each other are formed. Total thickness of a fourth upper cladding layer and a second contact layer of the second semiconductor laser is smaller than total thickness of a second upper cladding layer and the first contact layer of the first semiconductor laser. First and second ridges are formed in the first and second semiconductor lasers by dry etching, using a resist as a mask, and the dry etching is stopped when a second etching stopper layer is exposed at the second ridge. The second upper cladding layer remaining on a first etching stopper layer at the first ridge is selectively removed by wet etching, using the resist as a mask.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 16, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Nobuyuki Kasai
  • Patent number: 7670864
    Abstract: A CMOS image sensor and method of manufacture reduces the problem of electron loss in a floating diffusion area. A method of fabricating a CMOS image sensor includes forming a gate electrode over a first conductive type semiconductor substrate. A second conductive type first diffusion layer is formed within the semiconductor substrate to be aligned with an edge of one side of the gate electrode. A spacer may be attached to both sidewalls of the gate electrode. A first conductive type second diffusion layer may be formed within the first diffusion layer to leave a distance amounting to a width of the spacer in-between. A second conductive type third diffusion layer may be formed within the semiconductor substrate to be aligned with an edge of the other side of the gate electrode. A first conductive type fourth diffusion layer may be formed over the third diffusion layer, and a first conductive type fifth diffusion layer may be formed under the third diffusion layer.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: March 2, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Keun-Hyuk Lim