Abstract: An oscillation circuit is provided with a positive feedback oscillation loop constructed by an amplifier, a SAW resonator with a prescribed resonance frequency, a phase-shifting circuit which outputs the phase of an input signal as an output signal with a prescribed shift and a tank circuit composed of an inductance element and a capacitive element, and an NTC thermistor with negative temperature characteristics is connected in parallel to the tank circuit. Moreover, a capacitive element with a capacity-temperature characteristic for correcting the quadratic frequency-temperature characteristic of the SAW resonator is used in the oscillation circuit as the oscillation element of the tank circuit.

Abstract: A charge-pump circuit for charge-share suppression. A first switching element is coupled between a first connecting node and an output terminal. A first load receives a current from a first current source and outputs an output voltage at the output terminal when the first switching element is in “On” state. A status of a second switching element is controlled by the input signal and opposite to the status of the first switching elements A second current source is coupled to the second switching element through a second connecting node. A second load receives the output voltage when the second switching element is in “On” state. A first feedback circuit maintains a constant relation between the output voltage and a voltage of the first node. A second feedback circuit maintains a constant relation between the output voltage and a voltage of the second node.

Abstract: (Object) It was difficult for a feedforward amplifier to perform stable and high-speed distortion compensation control. (Constitution) It is a feedforward amplifier having CPL1 of dividing an input carrier signal into two output signals, VAP1 of adjusting one of the two divided output signals, AMP1 of amplifying the adjusted one of the output signals to generate an amplification signal, CPL2 of extracting a distortion signal by utilizing the other output signal of the two divided output signals and the generated amplification signal, CPL3 of generating an output carrier signal by utilizing the generated amplification signal and the extracted distortion signal, and CNT1 having a log amplifier of controlling VAP1 based on the other output signal and the generated amplification signal.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: According to the present invention, a variable delay circuit includes a delay circuit unit group, a control unit and an offset delay amount memory group. The delay circuit unit group includes a plurality of delay circuit units, and the plurality of delay circuit units includes two paths having different delay amounts. The offset delay amount memory group includes a plurality of offset delay amount memories, and offset delay amounts corresponding to delay amounts of the first paths of the corresponding delay circuit units are set in the plurality of offset delay amount memories. The control unit includes a plurality of subtracting units, and the plurality of subtracting units select paths of the delay circuit units through which an input signal may pass by using a delay setting value and offset delay amounts. It is possible to reduce volume of the circuit and remove a table since the path is selected by calculation.

Abstract: Delay lock loops (DLLs) that include delay line circuits with an optional clock pulse width restoration feature, and programmable delay circuits that enable the DLLs. A DLL can include optional inversions before and after at least one of the delay lines included in the DLL. Because two inversions are provided, the overall logic of the delay line is preserved. A DLL typically includes several different delay lines. Therefore, by selectively inverting the clock signal between the delay lines, the effect of each delay line on the clock pulse width can be balanced to provide an output clock signal having a pulse width closer to that of the input clock than would be achievable without the use of such selective inversion. In embodiments where the DLL forms a portion of a programmable logic device (PLD), the optional inversions can be controlled, for example, by configuration memory cells of the PLD.

Abstract: A signal pathway is presented for routing clock signals from a clock driving device to a circuit component and on to a termination. The signal pathway employs a minimal stub to carry the clock signals to the circuit component without introducing excess signal distortions. A first signal line of the signal pathway is formed on a circuit board and extends from the clock driving device to a first terminal for interfacing with the circuit component. A second signal line of the signal pathway is routed on the circuit component from one end adjacent to and electrically coupled with the first terminal to an opposite end adjacent to and electrically coupled with a second terminal formed on the circuit board. The stub extends from the second signal line on the circuit component. A third signal line of the signal pathway extends on the circuit board from the second terminal to the termination.

Abstract: The invention is a method and apparatus for coupling energy into or out of a dielectric resonator circuit by means of a coupling loop. More particularly, the invention is a method and apparatus for adjustably mounting a coupling loop relative to a resonator, the method and apparatus particularly adapted for use with conical and similar resonators in which the field of interest, typically the TE mode, varies as a function of longitudinal position relative to the resonator.

Abstract: A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit includes a first circuit coupled to receive the clock input and a second circuit coupled to receive the clock input and the condition signal. The first circuit is configured to generate a first state on the clock output responsive to a first phase of the clock input. The second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input. In one implementation, one or more of the conditional clock buffer circuits may be included in a clock tree. The clock tree may also include one or more levels of buffering.

Abstract: A high frequency amplifier in which a common emitter bipolar transistor is used, and in that a constant current source and a constant voltage source are switched to apply a DC bias to a base terminal of the bipolar transistor in accordance with a power level of a high frequency signal input to the bipolar transistor or a power level of a high frequency signal output therefrom, and a frequency mixer in that a DC bias is applied to a base of at least one of a bipolar transistor for the input of a high frequency signal and a bipolar transistor for the input of a local oscillation wave by using a configuration for applying the DC bias to a base of an amplifying bipolar transistor employed in the high frequency amplifier.

Abstract: The self-bias adjustment circuit is provided on the previous stage of an internal circuit. This self-bias adjustment circuit adjusts a bias of an input signal and supplies an appropriate signal to the internal circuit. The self-bias adjustment circuit includes a detection circuit 11a that detects the bias voltage of the input signal, and a superposing circuit 11b that superposes a correction voltage for correcting the bias voltage to a predetermined value on the input signal on the basis of the bias voltage detected by the detection circuit. The result signal is supplied to the internal circuit.

Abstract: A current-steering charge pump circuit and method for switch timing that reduces the amount of switching transients on an output current pulse produced by the charge pump. The current-steering type charge pump circuit includes four control signals, UP, UPB, DN and DNB. In order to produce an UP current pulse output signal, the UPB control signal is first asserted, followed by the UP control signal. After a period of time, which is proportional to the error signal that needs to be applied to a VCO, the UPB signal is first unasserted, followed by the UP signal. Similarly, to produce a DOWN current pulse output signal, a DN control is first asserted, followed by a DNB control signal. After a period of time, which is proportional to the error signal that needs to be applied to a VCO, the DN signal is first unasserted, followed by the DNB signal.

Abstract: In digital circuits, such as memory circuits, it is sometimes necessary to delay one signal a precise amount of time relative a reference signal. One way to do this is to feed the reference signal to a delay-locked loop which generates a set of signals, each delayed a different amount relative the reference signal. However, as circuits get faster and faster, conventional delay-locked loops require the addition of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal.

Abstract: To reduce the effect of the phase shift error originated from the mismatch of the delay units of the clock generator, we propose to add one more set of averaging amplifiers and averaging impedances, such as resistors, into the circuit of the clock generator. In the clock generator, outputs of all delay units connect to inputs of all averaging amplifiers respectively, and the averaging impedances connect the corresponding outputs of two adjacent averaging amplifiers, so as to form a closed loop. When a phase shift error occurs in the delay units, the averaging current through the averaging impedances will decrease the phase shift error in each stage. Specifically, the output impedance of the averaging amplifiers approaches infinite, and thus the resistance of the averaging impedances is relatively small. Therefore almost all signal currents will go through the averaging impedances, and an optimal averaging effect is achieved.

Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.

Abstract: A pulse-width modulation circuit comprises a comparator having hysteresis characteristics of positive feedback, and an integrator, whose integrated output is compared with an input signal to produce a pulse-width modulation (PWM) signal having an advanced phase characteristic due to differentiation of the input signal. A switching circuit amplifies the pulse-width modulation signal based on the positive and negative source voltages (VPX, VMX). The amplified pulse-width modulation signal is supplied to a speaker via an LC filter, and it is also negatively fed back to the pulse-width modulation circuit. Since the pulse-width modulation signal whose phase is advanced is transmitted through the LC filter, it is possible to reduce phase revolution in the output of the power amplifier circuit. Thus, it is possible to effect negative feedback on the pulse-width modulation signal in a stable manner.

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract: A frequency converter comprising a variable gain amplifier which amplifies the local oscillation signal according to a gain control signal and outputs an amplified local signal, an even harmonic mixer which is supplied with an input signal and an amplified local oscillation signal and outputs an output signal whose frequency is a sum of a first frequency of the input signal and a second frequency of two or more even numbered times a frequency of the amplified local oscillation signal, an amplitude detector which is supplied with the amplified local oscillation signal and outputs a direct current signal having an amplitude corresponding to an amplitude of the amplified local oscillation signal, and a comparator which compares the direct current signal of the amplitude detector with the reference direct current signal to generate an output signal as the gain control signal.

Abstract: A charge pump includes a first current source, a second current source, and a current mirror. The first current source is included to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core. The second current source is included to receive the common mode output voltage from the charge pump core. A first input of the current mirror receives a signal from the first current source, and a second input of the current mirror receives a signal from the second current source.