Abstract: An antenna 300 comprising a housing 310 with an internal cavity 315. The cavity 315 holds an adjustable amount of electrically conductive liquid, and a twin-conductor feedline 350 connects the antenna 300 to a receiving and/or transmitting device. The conductive liquid in the cavity 315 of the antenna housing 310 acts as a first element and receives/transmits signals from/to the first feedline conductor, whilst the second feedline conductor is attached to electrical ground 320.

Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

Abstract: A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.

Abstract: A processing circuit configured to: receive original data; partition the original data into a plurality of original q-bit words; assemble a data packet including N original q-bit words from the plurality of original q-bit words; identify a first encoder value and a second encoder value that are absent from the values of the N original q-bit words; encode the N original q-bit words based on a one-to-one mapping from q-bit original values to q-bit encoded values based on the first encoder value and the second encoder value to generate N encoded q-bit payload words, the N encoded q-bit payload words being free of words that are all-zeroes and free of words that are all-ones; generate a key representing the first encoder value and the second encoder value; and transmit the key and the N encoded q-bit payload words.

Abstract: A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

Abstract: A multiplexer includes a charging circuit; a plurality of sampling switches receiving a plurality of input signals; and a plurality of boosting circuits connected between the sampling switches and the charging circuit and sharing the charging circuit. First and second charging switches of the charging circuit are controlled by a first clock signal. Each of the boosting circuits includes a first boosting switch connected to a first node of the charging circuit and a gate of one of the sampling switches, a second boosting switch connected between a second node of the charging circuit and the one sampling switch, and a level shifter configured to control the first boosting switch and the second boosting switch in response to a second clock signal and a selection signal.

Abstract: An antenna component is provided. An orthographic projection of auxiliary antennas on a clearance area is entirely located in, partly located in, or close to a radiation-sensitive area where a specific absorption ratio (SAR) value of a frequency band needs to be reduced, so that a signal emitted from the radiation-sensitive area where the SAR value of the frequency band needs to be reduced on a primary antenna may be absorbed by the auxiliary antennas, and the auxiliary antennas generate secondary radiation.

Abstract: A first value of a first data element in a first set of data elements is obtained, the first set of data elements being based on a first time sample of a signal. A second value of a second data element in a second set of data elements is obtained, the second set of data elements being based on a second, later time sample of the signal. A measure of similarity is derived between the first value and the second value. Based on the derived measure, a quantisation parameter useable in performing quantisation on data based on the first time sample of the signal is determined. Output data is generated using the quantisation parameter.

Abstract: Embodiments herein describe a hardened fractional resampler that includes a fixed filter that supports simultaneous processing of N input samples with minimal additional combinational logic and no additional multipliers. In one embodiment, the fractional resampler is implemented in an integrated circuit using hardened circuit. The embodiments below exploit a pattern in the order filter phases in fractional resampling systems (such as a SSR resampling system) to use filter phases in a single fixed filter to process multiple input samples in parallel, where these filter phases would have been unused in previous resampling systems.

Abstract: An analog-to-digital (ADC) converter system and method of using the system that can be used in low power situations. The converter can periodically or recurrently turn off a reference standard in order to conserve power and instead using a stable supply source as a reference voltage. A precise conversion for signal from the analog to the digital domain while maintaining a low quiescent current.

Abstract: A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

Abstract: A vehicle identification means serve to identify vehicles by means of a unique identification. The protection of such identifications against falsification and tampering proves particularly problematic. For this purpose, known vehicle identification means have data carriers which can be read out in a contactless fashion and on which data for permitting unambiguous identification are stored. However, such identification means are very complex in design and are susceptible to faults. The invention provides an improved vehicle identification means which has a design which is as simple as possible and has a lower level of susceptibility to faults. This is ensured in that at least one NFC transponder which can be read out in a contactless fashion and has the purpose of near-field communication with a data carrier and an antenna is assigned to a registration number plate body, wherein at least part of the antenna is arranged in a breakthrough.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: Provided is a dynamic Huffman encoding method based on a sorting network. Compared with traditional dynamic Huffman coding solutions, the method implements sorting on the basis of the sorting network, therefore the sorting process is not only stable, but also may ensure a stable sorting result; and moreover, sorting steps and related operations are simpler, thereby greatly simplifying the sorting and iteration processes, and thus the sorting efficiency is higher. In addition, the sorting process better facilitates program implementation and transplantation, and implementation of hardware and software may achieve good effects. In addition, the present disclosure further provides a dynamic Huffman coding apparatus and device based on a sorting network, and a readable storage medium, and the technical effects thereof correspond to the technical effects of the above method.

Abstract: An NFC device that receive a data frame with a start pattern including first and second pattern signals, and a data pattern corresponding to the start pattern. The NFC device comprising an analog-to-digital converter which generates first and second input signals based on the first and second pattern signals, respectively, a modem that includes a first sub-matched filter which multiplies a first match signal by the first and second input signals to respectively calculate first and second result values of the first match signal and multiplies a second match signal by the first and second input signals to respectively calculate first and second result values of the second match signal. The first sub-matched filter determines reception of the start pattern when the first and second result values of the first match signal or the first and second result values of the second match signal exceed a predetermined start pattern threshold.

Abstract: Provided are an analog-to-digital (AD) converter, a sensor processing circuit, and a sensor system capable of improving responsiveness of feedback control. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to sensor before first output part outputs the first digital data.

Abstract: In an antenna, a first antenna element includes a first radiation conductor and a first feeder line. A second antenna element includes a second radiation conductor and a second feeder line. A second feeder line is coupled to the first feeder line such that a first component, which is a capacitance component or an inductance component, is dominant. A first coupler couples the first and second feeder lines such that a second component different from the first component is dominant. The first and second radiation conductors are arranged at interval of ½ or less of resonance wavelength. The second feeder line is coupled to the first radiation conductor such that a third component, which is the capacitance component or the inductance component, is dominant. The first coupling portion couples the first radiation conductor and the second feeder line such that a fourth component different from the third component is dominant.

Abstract: A system and method to convert a wideband optical signal to a multi-bit digital electrical signal using a superconducting integrated circuit. In a preferred embodiment, the optical signal modulates the phase (i.e., adjusts the timing) of a sequence of single-flux-quantum voltage pulses. The optoelectronic modulator may comprise an optically tunable Josephson junction, superconducting inductor, or bolometric detector, with switching speeds approaching 100 ps or less. The optical signal may comprise a plurality of optical signals such as a wavelength-division multiplexed signal. The optical-to-digital converter may be applied to high-speed digital communication switches, broadband digital input/output for superconducting or quantum computing, and control/readout of detector arrays.

Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

Abstract: A successive approximation analog-to-digital with an input for receiving an input analog voltage, and an amplifier with a first set of electrical attributes in a sample phase and a second set of electrical attributes, differing from the first set of electrical attributes, in a conversion phase.