Patents Examined by Linh V Nguyen
  • Patent number: 11923866
    Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: March 5, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsuan-Ting Ho, Shih-Hsiung Huang, Liang-Wei Huang
  • Patent number: 11923875
    Abstract: Provided is a dynamic Huffman encoding method based on a sorting network. Compared with traditional dynamic Huffman coding solutions, the method implements sorting on the basis of the sorting network, therefore the sorting process is not only stable, but also may ensure a stable sorting result; and moreover, sorting steps and related operations are simpler, thereby greatly simplifying the sorting and iteration processes, and thus the sorting efficiency is higher. In addition, the sorting process better facilitates program implementation and transplantation, and implementation of hardware and software may achieve good effects. In addition, the present disclosure further provides a dynamic Huffman coding apparatus and device based on a sorting network, and a readable storage medium, and the technical effects thereof correspond to the technical effects of the above method.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: March 5, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Zhen Qin, Tao Yuan, Zhen Wang, Jinfu Wang
  • Patent number: 11916563
    Abstract: Provided are an analog-to-digital (AD) converter, a sensor processing circuit, and a sensor system capable of improving responsiveness of feedback control. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to sensor before first output part outputs the first digital data.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: February 27, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Jun'Ichi Naka, Koji Obata, Junji Nakatsuka, Hiroki Yoshino, Masaaki Nagai
  • Patent number: 11916294
    Abstract: In an antenna, a first antenna element includes a first radiation conductor and a first feeder line. A second antenna element includes a second radiation conductor and a second feeder line. A second feeder line is coupled to the first feeder line such that a first component, which is a capacitance component or an inductance component, is dominant. A first coupler couples the first and second feeder lines such that a second component different from the first component is dominant. The first and second radiation conductors are arranged at interval of ½ or less of resonance wavelength. The second feeder line is coupled to the first radiation conductor such that a third component, which is the capacitance component or the inductance component, is dominant. The first coupling portion couples the first radiation conductor and the second feeder line such that a fourth component different from the third component is dominant.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: February 27, 2024
    Assignee: KYOCERA CORPORATION
    Inventor: Hiromichi Yoshikawa
  • Patent number: 11916566
    Abstract: An NFC device that receive a data frame with a start pattern including first and second pattern signals, and a data pattern corresponding to the start pattern. The NFC device comprising an analog-to-digital converter which generates first and second input signals based on the first and second pattern signals, respectively, a modem that includes a first sub-matched filter which multiplies a first match signal by the first and second input signals to respectively calculate first and second result values of the first match signal and multiplies a second match signal by the first and second input signals to respectively calculate first and second result values of the second match signal. The first sub-matched filter determines reception of the start pattern when the first and second result values of the first match signal or the first and second result values of the second match signal exceed a predetermined start pattern threshold.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae Hun Choi
  • Patent number: 11906877
    Abstract: A system and method to convert a wideband optical signal to a multi-bit digital electrical signal using a superconducting integrated circuit. In a preferred embodiment, the optical signal modulates the phase (i.e., adjusts the timing) of a sequence of single-flux-quantum voltage pulses. The optoelectronic modulator may comprise an optically tunable Josephson junction, superconducting inductor, or bolometric detector, with switching speeds approaching 100 ps or less. The optical signal may comprise a plurality of optical signals such as a wavelength-division multiplexed signal. The optical-to-digital converter may be applied to high-speed digital communication switches, broadband digital input/output for superconducting or quantum computing, and control/readout of detector arrays.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 20, 2024
    Assignee: SeeQC, Inc.
    Inventors: Oleg A. Mukhanov, Igor V. Vernik
  • Patent number: 11909410
    Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Sharad Gupta
  • Patent number: 11901910
    Abstract: A successive approximation analog-to-digital with an input for receiving an input analog voltage, and an amplifier with a first set of electrical attributes in a sample phase and a second set of electrical attributes, differing from the first set of electrical attributes, in a conversion phase.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: February 13, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishnaswamy Nagaraj, Joonsung Park
  • Patent number: 11901907
    Abstract: An electronic device includes analog-to-digital converters each configured to receive an analog input signal and output a digital output signal corresponding to the analog input signal, an analog input signal generator configured to generate analog input signals provided to each analog-to-digital converter based on input voltages and weight data, an input signal distribution information generator configured to generate input signal distribution information indicating a distribution of the analog input signals for each of the analog-to-digital converters, an analog-to-digital converter group classifier configured to classify the analog-to-digital converters into a plurality of first analog-to-digital converter groups based on the input signal distribution information, and an analog-to-digital converter input range optimizer configured to determine an input range of each first analog-to-digital converter group based on the input signal distribution information, and each analog-to-digital converter is configured
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: February 13, 2024
    Assignee: SK HYNIX INC.
    Inventors: Sang Eun Je, Ki Young Kim
  • Patent number: 11888494
    Abstract: A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: January 30, 2024
    Assignee: Nuvoton Technology Corporation Japan
    Inventors: Masao Iriguchi, Yosuke Goto
  • Patent number: 11888498
    Abstract: Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: January 30, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Daniel H. Saari, Lewis F. Lahr
  • Patent number: 11888497
    Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: January 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Pranav Sinha, Meghna Agrawal
  • Patent number: 11888499
    Abstract: A transition-state output device includes: a ring oscillator circuit; a state machine changing in state according to a change in state of the ring oscillator circuit; a transition-state acquisition section acquiring and holding state information including a signal output from the ring oscillator circuit and a signal output from the state machine, synchronously with a reference signal; and an internal-state calculation section calculating an internal state corresponding to a number of changes in state of the ring oscillator circuit, based on the state information held by the transition-state acquisition section. A time until the internal state, after transitioning from a first internal state to a second internal state, transitions to the first internal state again is longer than a time interval of updating the state information held by the transition-state acquisition section.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: January 30, 2024
    Inventor: Masayoshi Todorokihara
  • Patent number: 11880368
    Abstract: A method includes determining a data set for storage that includes a plurality of uncompressed data slabs in accordance with a serialized data slab ordering. A storage data set that includes a plurality of compressed data slabs is created based on the data set in accordance with the serialized data slab ordering. Each compressed data slab of the plurality of compressed data slabs is generated from at least one corresponding uncompressed data slab of the plurality of uncompressed data slabs that includes a plurality of values based on generating compressed data for each compressed data slab based on the at least one corresponding uncompressed data slab, and generating compression information for each compressed data slab. The storage data set is stored via a plurality of computing devices.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 23, 2024
    Assignee: Ocient Holdings LLC
    Inventor: George Kondiles
  • Patent number: 11881868
    Abstract: A control system includes: a semiconductor chip, having built therein a processing part, an A/D converter and a pull device circuit; a wiring part, having one end connected to a terminal connected to the A/D converter; and a sensor, connected to the other end of the wiring part and inputting a sensor signal in analog form via the wiring part. The pull device circuit includes a switching element, and has one end connected to ground or a power supply voltage and the other end connected between the A/D converter and the terminal. The processing part includes: a switch control part, controlling the switching element to be in an on or off state; a sensor information generator, generating sensor information based on the sensor signal; and a disconnection detector, detecting disconnection of the wiring part based on output of the A/D converter when the switching element is in the on state.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: January 23, 2024
    Assignee: MITSUBA Corporation
    Inventor: Miya Yamada
  • Patent number: 11876526
    Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: January 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsiung Huang, Kai-Yue Lin, Wei-Jyun Wang, Sheng-Yen Shih
  • Patent number: 11870413
    Abstract: An antenna structure includes a first antenna radiator, a second antenna radiator, a first impedance matching circuit, a second impedance matching circuit, and a signal source, wherein the first antenna radiator is coupled to the second antenna radiator by means of a slot; the end of the first antenna radiator away from the slot is grounded, and the first antenna radiator is provided with a feed point, the end of the second antenna radiator away from the slot is grounded; a first end of the first impedance matching circuit is connected to the feed point, and a second end of the first impedance matching circuit is connected to a first end of the signal source; a first end of the second impedance matching circuit is connected to a third end of the first impedance matching circuit, and a second end of the second impedance matching circuit is grounded.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: January 9, 2024
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventor: Rihui Li
  • Patent number: 11870467
    Abstract: A data compression method, comprising: obtaining a plurality of values of a parameter and an occurrence probability of each of the plurality of values (S101); comparing the occurrence probability with a predetermined threshold, wherein values with the occurrence probability less than the predetermined threshold are first set of values, and values with the occurrence probability greater than or equal to the predetermined threshold are second set of values (S102); performing pretreatment on the first set of values (S103); and encoding the second set of values and the pretreated first set of values (S104). By means of the data compression method, the maximum codeword length can be effectively reduced, so as to reduce the requirements of a code table to the storage space.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: January 9, 2024
    Inventors: Bing Xu, Nangeng Zhang
  • Patent number: 11870446
    Abstract: In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Henderson Perrott, Hon Kin Chiu
  • Patent number: 11868305
    Abstract: Disclosed is a processor chip that includes on-chip and off-chip software. The chip is optimized for hyperdimensional, fixed-point vector algebra to efficiently store, process, and retrieve information. A specialized on-chip data-embedding algorithm uses algebraic logic gates to convert off-chip normal data, such as images and spreadsheets, into discrete, abstract vector space where information is processed with off-chip software and on-chip accelerated computation via a desaturation method. Information is retrieved using an on-chip optimized decoding algorithm. Additional software provides an interface between a CPU and the processor chip to manage information processing instructions for efficient data transfer on- and off-chip in addition to providing intelligent processing that associates input information to allow for suggestive outputs.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: January 9, 2024
    Inventor: Rachel St. Clair