Patents Examined by Lisa Sievers
  • Patent number: 7376529
    Abstract: A valve tester system is disclosed that comprises a valve tester assembly for rotating a valve stem of a valve. The valve tester assembly may include a support, a rotation element mounted on the support for rotating a valve during a rotation event, a control element for controlling aspects of the rotation event of the valve by the rotation element, and an element for detecting a location of the valve tester assembly during the rotation event of the valve. In some embodiments of the invention, the element for detecting the location of the valve tester assembly includes a Global Positioning Satellite (GPS) receiver. In some embodiments, the GPS receiver is integral with the control element.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: May 20, 2008
    Inventor: Lyndon J. Hurley
  • Patent number: 7369963
    Abstract: A system managing apparatus that monitors a status of a device, which is installed in an information processing apparatus, includes a connecting unit that connects the system managing apparatus with other system managing apparatus installed in other information processing apparatus to exchange information; and a monitoring-target switching unit that switches a device to be monitored from a device connected to the system managing apparatus to other device connected to the other system managing apparatus.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 6, 2008
    Assignee: Fujitsu Limited
    Inventor: Toshio Yasutake
  • Patent number: 7356420
    Abstract: Analyzing system for the detection of reducing and oxidizing gases in a carrier gas, wherein the detection means are sensors based on semiconductor-type metal oxides that work in the absence of oxygen. The system includes means for connecting to a chamber which contains the sensors, and moreover in that the processing and control include a system of real-time recognition of the gases, which provides a diagram in which the measurements taken on the carrier gas are situated and identified. The analyzing system permits analysis of the gas in real time.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: April 8, 2008
    Assignee: Sociedad Epanola De Carburos Metalicas, S.A.
    Inventors: Xavier Vilanova, Xavier Correig, Eduard Llobet, Jesús Brezmes, Raul Calavia, Xavier Sanchez
  • Patent number: 7337085
    Abstract: Disclosed is method and device for compensating a force sensor signal for baseline error in a force-based touch screen. In one embodiment, baseline compensation includes determining a decaying maximum value and a decaying minimum value of the force sensor signal, and subtracting these values to obtain a range value. When the range value is less than a predetermined activity threshold, updating of the baseline is disabled. The decaying maximum value and decaying minimum value are reset to the current value of the force sensor signal when exceeded by the current value of the force sensor signal.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: February 26, 2008
    Assignee: QSI Corporation
    Inventor: David A. Soss
  • Patent number: 7333904
    Abstract: A processor is responsive to a thermistor temperature (Tth) adjacent a FET and to a drain-to-source voltage (VDS) of the FET. The processor stores the characteristics of the PET and a thermal model of the system hardware and uses a first set of equations to determine the temperature (TJ) at the junction of the PET in a stable region of operation where TJ?Tth is nearly constant. The processor is further responsive to a step change in successive measurements of VDS indicative of a lag of Tth relative to TJ. In this step-change region, the processor then resolves TJ based upon a second set of equations.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: February 19, 2008
    Assignee: Delphi Technologies, Inc.
    Inventors: Steven R. Turner, Mohammad Zakaria
  • Patent number: 7313500
    Abstract: A manufacturer determines a maximum ambient temperature for an electronic device to be manufactured. The device has a data processor equipped with a utilization monitor. A test unit of the device is manufactured and placed under test at the maximum ambient temperature. The manufacturer during this test stage runs the application software for the electronic device at this time, in the test state. The temperature of the processor and its utilization reading are observed If the processor temperature increases out of range, then the software should be changed to utilize less processing capacity of the processor. A suitable reduction or adjustment in the software is determined, and the utilization amount is stored in memory. The electronic device is constructed with the alert circuitry and process. Hence, if the user should task the processor beyond the predetermined limit, the electronic device communicates that to the user.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: December 25, 2007
    Assignee: Schweitzer Engineering Labortories, Inc.
    Inventor: Daniel N. Morman
  • Patent number: 7313496
    Abstract: A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: December 25, 2007
    Assignee: Advantest Corporation
    Inventors: Masahiro Ishida, Takahiro Yamaguchi, Mani Soma
  • Patent number: 7305326
    Abstract: A method is disclosed for acquisition and analysis of condition monitoring data. Alarm and alert limits are set to proper levels and information regarding the frequency and cause for alerts is collected. Analysis of the information may then be performed to provide a user with easily understandable representations of the system errors and suggested actions.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: December 4, 2007
    Assignee: CSI Technology, Inc.
    Inventors: Anthony J. Hayzen, Raymond E. Garvey, Andrew Carey, Kenneth R. Piety
  • Patent number: 7289934
    Abstract: A semiconductor device includes an output driver circuit for generating noise on wiring for a power supply using a trigger signal input from measuring equipment and a noise measuring circuit. The noise measuring circuit includes a comparator circuit for comparing a voltage on wiring for the power supply with a reference voltage supplied from the measuring equipment and outputting a result of comparison, and two latch circuits for respectively holding the change of the result of comparison to one state and the change of the result of comparison to the other state, for output to the measuring equipment. The measuring equipment changes the reference potential, monitors times from a change of the trigger signal which becomes a trigger for noise generation, to changes of output signals of the two latch circuits, and plots the reference voltage and timings of the output changes, thereby estimating the waveform of the noise.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: October 30, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Yasufumi Suzuki
  • Patent number: 7289926
    Abstract: The present invention provides for a method for examining high-frequency clock-masking signal patterns at a reduced frequency. A first mode of a first shift register is selected. A plurality of bits is loaded on the first shift register at a first frequency. A second mode of the first shift register is selected. A first mode of a second shift register is selected. The plurality of bits is loaded on the second shift register. A second mode of the second shift register is selected. A first mode of a third shift register is selected. The plurality of bits is loaded on the third shift register. A second mode of the third shift register is selected and the plurality of bits is loaded from the third shift register at a second frequency, where the second frequency is lower than the first frequency, thereby providing for examining high-frequency clock-masking signal patterns at a reduced frequency.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Jieming Qi
  • Patent number: 7283920
    Abstract: A phase difference between a timing of rising or falling of the data read from a semiconductor device to be test and a timing of rising or falling of a reference clock outputted synchronized with the data is measured by operating sampling with strobe pulses configured with multi-phase pulses given the phase difference by a small amount in regard to the timing of the data and the timing of the reference clock. In addition, a glitch of the data is detected, and the quality of the semiconductor device to be tested is judged based on the phase difference and/or the glitch.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: October 16, 2007
    Assignee: Advantest Corporation
    Inventors: Masaru Doi, Takeo Miura
  • Patent number: 7280936
    Abstract: A system (400, 500) and method (800) of personal inertial navigation measurements can include measuring (802) an angle, measuring (804) an angular velocity independent of an angle measurement, measuring (806) an angular acceleration independent of the angle measurement and independent of an angular velocity measurement, and combining (808) the angle measurement, the angular velocity measurement, and an angular acceleration to provide an angled output. The angle measurement can be measured using a compass or magnetic field, the angular velocity can be measured using a gyroscope (such as a MEMS gyroscope), and the angular acceleration measurement can be measured using an angular accelerometer (such as a molecular electronic transfer device having a magneto hydrodynamic effect device). The method can further include suppressing (810) noise caused by the angle measurement by using a sample and hold circuit (504) controlled by a higher ordered component to suppress noise from a lower ordered component.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: October 9, 2007
    Assignee: Motorola, Inc.
    Inventors: Charles B. Swope, Daniel A. Tealdi
  • Patent number: 7272517
    Abstract: A method and system for providing performance estimations for a specified power budget provides an indication of the impact on processing performance when closed-loop power/performance control is employed to meet the specified power budget. A workload, which may be the actual workload, or a test workload is run to determine actual power consumption at intervals during the execution of the workload. The power values are examined and if they exceed the specified budget, which may be one of multiple possible budget values, an estimate of the amount by and duration for which the closed-loop power/performance control would have to reduce the performance of the system for each interval in order to provide an estimate of actual performance for the budgetary level(s). The estimate is informed by tests of the workload at each power/performance level to provide a non-linear estimate of the relationship between performance and power for the particular workload.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: September 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Brey, Wesley M. Felter, Charles R. Lefurgy, Karthick Rajamani, Juan C. Rubio, Malcolm S. Ware
  • Patent number: 7266474
    Abstract: A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: September 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Habitz, Jerry D. Hayes
  • Patent number: 7266465
    Abstract: An apparatus for confirming a frequency measurement of a received signal includes a discrete Fourier transform (DFT) module for receiving a sampled digital signal. The DFT module is configured to analyze the received sampled digital signal, and output amplitude values at different frequency components. A threshold comparator is included for receiving the amplitude values of the frequency components and outputting a thresholded-amplitude value exceeding a predetermined threshold value. A frequency confirmation is provided based on the thresholded-amplitude value. The sampled digital signal is sampled at a sampling frequency of fs, and the DFT module is configured to analyze the received sampled digital signal at a frequency bandwidth that is equal to or less than fs. The frequency bandwidth is equal to the sampling frequency of fs, when the received sampled digital signal includes I and Q signals.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: September 4, 2007
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: James B. Y. Tsui, Charles Richard Ward, Stuart Mitchell Lopata
  • Patent number: 7263447
    Abstract: An equipment status monitoring system and method of operating thereof is described. The equipment status monitoring system includes at least one microwave mirror in a plasma processing chamber forming a multi-modal resonator. A power source is coupled to a mirror and configured to produce an excitation signal extending along an axis generally perpendicular to a substrate. A detector is coupled to a mirror and configured to measure an excitation signal. A control system is connected to the detector that compares a measured excitation signal to a normal excitation signal in order to determine a status of the material processing equipment.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: August 28, 2007
    Assignee: Tokyo Electron Limited
    Inventor: Eric J. Strang
  • Patent number: 7251569
    Abstract: Methods, systems, and computer program products for analyzing a product are disclosed. The product includes parts supplied by suppliers. Each part includes materials, each material includes substances, and each substance has a respective substance amount. A database includes relationship information for the product, parts, materials, substances and substance amounts. The product is analyzed by, first, receiving instructions to select at least one of the product, the parts, or the materials for analysis. Next, responsive to the received instructions, relationship information is retrieved from the database for the selected product, parts, and materials. Finally, the retrieved relationship information is processed to determine at least one of (1) a materials breakdown or (2) a compliance status for the selected product, parts, or materials.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: July 31, 2007
    Assignee: Synapsis Enterprise LLC
    Inventors: P. German Avila, William F. Hoffman, III, Kurk W. Kan, Andrew M. Wertkin
  • Patent number: 7233871
    Abstract: A technique for developing an inspection program for a circuit board to be run on an AOI system includes determining a characteristic, such as average gray level, of each window of the circuit board. The positions of the windows are varied slightly to simulate expected errors in the placement of the windows relative to the circuit board. After varying the positions of the windows, the characteristic of each window is determined again. Different values of the characteristic corresponding to slightly different positions are compared for each window. Values that substantially change for a window indicate a strong sensitivity to position. These windows may be reported to a programmer for corrective action.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: June 19, 2007
    Assignee: Landrex Technologies Co., Ltd.
    Inventors: Douglas W. Raymond, Richard D. Fleming, John Haddon, Dominic F. Haigh
  • Patent number: 7206707
    Abstract: An IFM receiver includes a hybrid for outputting I and Q signals from a received input signal; a first ADC for digitizing the I signal to produce a first digital signal at a sampling rate of 1/?, and a second ADC for digitizing the Q signal to produce a second digital signal at the same sampling rate. A processor is configured to (a) delay the first and second digital signals by at least one sample time of ?, (b) count the number of samples produced having predetermined phase shifts, and (c) determine the frequency of the received input signal, based on the number of samples having the predetermined phase shifts. The first and second ADCs are each 1-bit analog-to-digital converters. The predetermined phase shifts of 0°, 90°, ?90° and 180° are counted by the processor over a predetermined time interval.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 17, 2007
    Assignee: ITT Manufacturing Enterprises Inc.
    Inventors: James B. Y. Tsui, Stuart Mitchell Lopata, Charles Richard Ward
  • Patent number: 7181347
    Abstract: Method and apparatus for predicting surface multiples, which includes (a) selecting a target subsurface line (SSL); (b) selecting an input SSL within an aperture of the target SSL; (c) selecting a point on a line twice the distance between the input SSL and the target SSL, the point corresponding to a potential downward reflection point of the surface multiples for a trace; (d) generating a potential surface multiple for the trace corresponding to the point; (e) repeating steps (c) through (d) for each point on the line to generate an inline of potential surface multiples corresponding to each point on the line; (f) repeating steps (b) through (e) for each input SSL within the aperture of the target SSL to generate potential surface multiples for the trace corresponding to each input SSL within the aperture; and (g) adding the potential surface multiples to generate a surface multiple for the trace.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: February 20, 2007
    Assignee: Westerngeco, L.L.C.
    Inventor: Ian Moore