Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a light sensing feature, a negative oxide layer, a gate dielectric layer and a transfer gate. The light sensing feature is configured in the substrate to detect an incoming radiation. The negative oxide layer is over the light sensing feature. The gate dielectric layer is over the negative oxide layer. The transfer gate is over the gate dielectric layer.

Abstract: A semiconductor device includes a gate electrode having higher Gibbs free energy for oxidation than a gate insulating film. An oxide semiconductor layer having a fin shape is formed over an insulating surface, a gate insulating film is formed over the oxide semiconductor layer, a gate electrode including an oxide layer and facing top and side surfaces of the oxide semiconductor layer with the gate insulating film located therebetween is formed, and then by performing heat treatment, a gate electrode is reduced and oxygen is supplied to the oxide semiconductor layer through the gate insulating film.

Abstract: Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The first package includes a first die. The method further includes attaching a first sensor to the first package and the first substrate. The first sensor is electrically coupled to the first package and the first substrate.

Abstract: A light-emitting device includes: a photoluminescent layer that emits light; and a light-transmissive layer on which the emitted light is to be incident. At least one of the photoluminescent layer and the light-transmissive layer defines a surface structure. The surface structure has projections and/or recesses to limit a directional angle of the emitted light. The photoluminescent layer and the light-transmissive layer are curved.

Abstract: A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Subsequently, a trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting board, and then a thinning process and a deposition process of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting board is removed and a plurality of contacting pads is formed. A cutting process is performed along the cutting portion.

Abstract: Provided are an epitaxial wafer and a method of fabricating the same. The method includes a pre-growth step of injecting a reaction source for epitaxial growth on a semiconductor wafer prepared in a chamber and growing an epitaxial layer by a predetermined first thickness at a predetermined first growth rate and at a predetermined first growth temperature, a heat treatment step of performing heat treatment on the epitaxial layer grown by the pre-growth step during a predetermined time, and a subsequent growth step of injecting the reaction source on the heat-treated semiconductor wafer and growing the epitaxial layer to a target thickness at a predetermined second growth rate and at a predetermined second growth temperature. The first growth rate is smaller than the second growth rate.

Abstract: A random access point is generated in a stream of coded digital pictures containing a plurality of predictive coded frames that have two or more predictive coded frames in which one or more subsections of each of the two or more predictive coded frames are intra coded. Information is added to a stream of digital pictures that identifies for a decoder which of two or more predictive-coded frames in the stream have intra-coded subsections at different portions that can be combined to form a patch frame.

Abstract: A package structure with an optical barrier is provided. An emitter for emitting an optical signal and a detector for receiving the optical signal are disposed on a substrate. The optical barrier is disposed between the emitter and the detector for shielding the excess optical signal. A package material is used to completely cover the optical barrier, the emitter and the detector so that the optical barrier is completely disposed within the package material.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a memory cell structure formed over the substrate. In addition, the memory cell structure includes a first electrode layer formed over the substrate and a resistance-change material layer formed over the first electrode layer. The memory cell structure further includes a second electrode layer formed over the resistance-change material layer. In addition, the resistance-change material layer includes a semimetal or a semimetal alloy.

Abstract: To provide a transistor having highly stable electric characteristics and also a miniaturized structure. Further, also high performance and high reliability of a semiconductor device including the transistor can be achieved. The transistor is a vertical transistor in which a first electrode having an opening, an oxide semiconductor layer, and a second electrode are stacked in this order, a gate insulating layer is provided in contact with side surfaces of the first electrode, the oxide semiconductor layer, and the second electrode, and a ring-shaped gate electrode facing the side surfaces of the first electrode, the oxide semiconductor layer, and the second electrode with the gate insulating layer interposed therebetween is provided. In the opening in the first electrode, an insulating layer in contact with the oxide semiconductor layer is embedded.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.

Abstract: A high voltage integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region defined in the semiconductor layer and between the source region and the drift region, a trench insulation field plate disposed in the drift region, a recessed region provided in the trench isolation field plate, a metal field plate disposed over the trench insulation field plate, and filling the recessed region, a gate insulation layer provided over the channel region and extending over the drift region and over the trench insulation field plate, and a gate electrode disposed over the gate insulation layer.

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate. The isolation region surrounds an active region of the substrate in plan view and includes an insulating material. A first dielectric layer is formed over the active region. A mask layer is formed on at least a part of a border line between the isolation region and the active region. The mask layer covers a part, but not entirety, of the first dielectric layer and a part of the isolation region surrounding the active region. The first dielectric layer not covered by the mask layer is removed such that a part of the active region is exposed. After the first dielectric layer is removed, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. A gate electrode is formed over the gate dielectric layer.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

Abstract: An integrated circuit (IC) using high-? metal gate (HKMG) technology with an embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. The logic gate is arranged within a high ? dielectric layer. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate. The control transistor further comprises a charge trapping layer underlying the control gate. The control and select gates are a first material, and the logic gate is a second material. A high-?-last method for manufacturing the IC is also provided.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a memory region. The memory region comprises a bottom via, a recap layer on the BV, a bottom electrode on the recap layer, a magnetic tunneling junction layer on the bottom electrode, and a top electrode on the MTJ layer. The material of the recap layer is different from that of the BV.

Abstract: Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.

Abstract: A method of processing a semiconductor substrate is provided. The method may include forming a film over a first side of a semiconductor substrate, forming at least one separation region in the semiconductor substrate between a first region and a second region of the semiconductor substrate, arranging the semiconductor substrate on a breaking device, wherein the breaking device comprises a breaking edge, and wherein the semiconductor substrate is arranged with the film facing the breaking device and in at least one alignment position with the at least one separation region aligned with the breaking edge, and forcing the semiconductor substrate to bend the first region with respect to the second region over the breaking edge until the film separates between the breaking edge and the at least one separation region.

Abstract: Provided is a thin film transistor (TFT) that includes a first electrode on a substrate separated from a second electrode, an oxide semiconductor pattern on the second electrode including a channel region, a third electrode on the oxide semiconductor pattern, a first insulating layer on the substrate including the third electrode including first contact holes exposing a part of the first electrode, a part of the second electrode, and a part of the third electrode, a gate electrode on the first insulating layer and corresponding to a part of the oxide semiconductor pattern, a second insulating layer on the substrate including the gate electrode including a second contact hole corresponding to the first contact hole that exposes a part of the second electrode, and a pixel electrode on the second insulating layer electrically connected to the second electrode through the first contact hole and the second contact hole.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.