Abstract: In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.

Abstract: A gallium nitride based semiconductor diode includes a substrate, a GaN layer formed on the substrate, an AlGaN layer formed on the GaN layer where the GaN layer and the AlGaN layer forms a cathode region of the diode, a metal layer formed on the AlGaN layer forming a Schottky junction therewith where the metal layer forms an anode electrode of the diode, and a high barrier region formed in the top surface of the AlGaN layer and positioned under an edge of the metal layer. The high barrier region has a higher bandgap energy than the AlGaN layer or being more resistive than the AlGaN layer.

Abstract: The disclosure facilitates testing and binning of multiple LED chip or other optoelectronic chip packages fabricated on a single semiconductor wafer. The testing can take place prior to dicing. For example, in one aspect, metallization on the front-side of a semiconductor wafer electrically connects together cathode pads (or anode pads) of adjacent sub-mounts such that the cathode pads (or anode pads) in a given column of sub-mounts are electrically connected together. Likewise, metallization on the back-side of the wafer electrically connects together anode pads (or cathode pads) of adjacent sub-mounts such that the anode pads (or cathode pads) in a given row of sub-mounts are electrically connected together. Probe pads, which can be located one or both sides of the wafer, are electrically connected to respective ones of the rows or columns.

Abstract: An organic-field effect transistor, a method of manufacturing the same, and a flat panel display device including the organic-field effect transistor. The organic-field effect transistor includes an organic semiconductor layer, a gate electrode, and a charge carrier blocking layer. The charge carrier blocking layer is interposed between the gate electrode and the organic semiconductor layer, and it comprises a semiconducting material.

Abstract: A thin film transistor array panel, in which a middle storage electrode and a storage electrode overlapping a drain electrode of a thin film transistor thereby forming a storage capacitance are formed. Accordingly, sufficient storage capacitance may be formed without a decrease of the aperture ratio and fight transmittance of a liquid crystal display. Also, the capacitance may be sufficiently formed through the connecting member connected to a gate metal layer.

Abstract: In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

Abstract: A stacked semiconductor package and a method for manufacturing the same. The stacked semiconductor package includes a semiconductor chip module having two or more semiconductor chips which are stacked in the shape of steps. Each of the semiconductor chips includes pads located on an upper surface thereof and an inclined side surface connected with the upper surface. Connection patterns are formed in the shape of lines on the inclined side surfaces and the upper surfaces of the semiconductor chips to electrically connect pads of the semiconductor chips.

Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Abstract: The present invention relates to a depletion or enhancement mode metal transistor in which the channel region of a transistor device comprises a thin film metal or metal composite layer formed over an insulating substrate.

Abstract: A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: An organic light emitting display device and a driving method for the same is provided. The device includes a data driver that can cause a display of an image having a uniform luminance. The data driver includes a ramp pulse generating part for generating a ramp pulse. The data driver also includes a current digital-to-analog converting part for generating a data current using data provided to the data driver. The data driver also includes a current control part for providing the ramp pulse to data lines coupled to a pixel and comparing a pixel current from the pixel with the data current to control providing of the ramp pulse to the data lines. The pixel current corresponds to the ramp pulse.

Abstract: A nanowire, nanosphere, metallized nanosphere, and methods for their fabrication are outlined. The method of fabricating nanowires includes fabricating the nanowire under thermal and non-catalytic conditions. The nanowires can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the method of fabricating nanospheres includes fabricating nanospheres that are substantially monodisperse. Further, the nanospheres are fabricated under thermal and non-catalytic conditions. Like the nanowires, the nanospheres can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the nanospheres can be metallized to form metallized nanospheres that are capable as acting as a catalyst.

Abstract: A display device where the influence of variations in current of the light emitting element due to changes in ambient temperature and changes with time can be suppressed. The display device of the invention has a light emitting element, a driving transistor connected in series to the light emitting element, a monitoring light emitting element, a limiter transistor connected in series to the monitoring light emitting element, a constant current source for supplying a constant current to the monitoring light emitting element, and a circuit for outputting a potential equal to an inputted potential. A first electrode of the light emitting element is connected to an output terminal of the circuit through the driving transistor, and a first electrode of the monitoring light emitting element is connected to an input terminal of the circuit through the limiter transistor.

Abstract: Embodiments of the present invention provide pixel cells with increased storage capacity, which are capable of anti-blooming operations. In an exemplary embodiment a pixel cell has an electronic shutter that transfers charge generated by a photo-conversion device to a storage node before further transferring the charge to the pixel cell's floating diffusion node. Each pixel cell also includes an anti-blooming transistor for directing excess charge out of each respective pixel cell, thus preventing blooming. Additionally, two or more pixel cells of an array may share a floating diffusion node and reset and readout circuitry.

Abstract: An organic light emitting display device and a method of fabricating the same are provided. The organic light emitting display device includes a substrate, a first electrode formed on the substrate, an inorganic pixel defining layer formed on the first electrode and having an opening exposing at least a portion of the first electrode, an organic layer disposed on the first electrode and having at least an organic emission layer, and a second electrode formed on the organic layer.

Abstract: A semiconductor memory device includes a first well region of a first conductivity type, first and second SRAM cells adjacently arranged to each other, the first and second SRAM cells each including at least a first transfer transistor and a drive transistor formed on the first well, the first transfer transistor and the drive transistor being coupled in series between a bit line and a power source line, and a first diffusion region of the first conductivity type arranged between the drive transistor of the first SRAM cell and the drive transistor of the second SRAM cell, to apply a first well potential to the first well.

Abstract: A semiconductor device includes a semiconductor substrate and an alignment mark. The alignment mark is provided on the semiconductor substrate and optically detectable. The alignment mark includes a bright area and a dark area. The bright area outputs light reflected from a surface of the semiconductor substrate. The dark area includes metal wirings, outputs light reflected from surfaces of the metal wirings, and has brightness lower than that of the bright area.

Abstract: A method and apparatus for generating haptic effects for a touch panel or other interface device employs a touch-sensitive panel, a display and an actuator. The actuator includes a first structural element and a second structural element, a biasing element and two magnetic devices. The first magnetic device is configured to be carried by the first structural element and the second magnetic device is configured to be carried by the second structural element. The first structural element is coupled to a touch-sensitive panel and the second structural element may be coupled to the display or to a relatively fixed item. The biasing element couples the first and second structural elements together and deforms to facilitate a movement between the first and second structural elements. The actuator provides haptic effects by facilitating relative movement between the first and second structural elements.

Abstract: A liquid crystal display device includes a timing control unit for generating first and second control signals, which are transitioned every ½ frame. A polarity signal is set according to a count number obtained by counting the number of wave forms of the first and/or second control signals. A plurality of gate lines and data lines are arranged on a substrate crossing each other. A plurality of pixels are arranged in a matrix format on the substrate, with two pixels being provided in the regions divided by the gate and data lines. A data driving unit determines polarities of the first and second image data according to the polarity signal being received from the timing control unit, and then supplies the first and second image data to the pixels in the first and second columns through the first and second data lines, respectively.

Abstract: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer.