Abstract: An integrated circuit multiplier-accumulator architecture includes an M-bit wide register for inputting an X operand and an N-bit wide input register for inputting a Y operand to a multiplier. The multiplier can selectably multiply or concatenate the operands to produce a binary product in the form of a first array of M+N parallel bits. A binary adder adds the binary product to a second array of M+N+P+1 parallel bits and outputs the sum as a Z result in the form of a third array of M+N+P+1 parallel bits. The Z result is stored in a selected one of two accumulators. A feedback path is provided to output selected accumulator contents to the adder as the second binary array of M+N+P+1 bits. Output ports are provided for outputting a selected portion of the accumulator contents. Preferably, the output ports can output the entire M+N+P bits in parallel, as well as any selected portion thereof.