Abstract: A lens and encapsulant made of an amorphous fluoropolymer for a light-emitting diode (LED) or diode laser, such as an ultraviolet (UV) LED (UVLED). A semiconductor diode die (114) is formed by growing a diode (110) on a substrate layer (115) such as sapphire. The diode die (114) is flipped so that it emits light (160, 365) through the face (150) of the layer (115). An amorphous fluoropolymer encapsulant encapsulates the emitting face of the diode die (114), and may be shaped as a lens to form an integral encapsulant/lens. Or, a lens (230, 340) of amorphous fluoropolymer may be joined to the encapsulant (220). Additional joined or separate lenses (350) may also be used. The encapsulant/lens is transmissive to UV light as well as infrared light. Encapsulating methods are also provided.

Abstract: The present invention relates to a method of manufacturing a flat aluminum electrolytic capacitor comprising a separator impregnated with an electrolytic solution, an anode foil and a cathode foil, a flat capacitor element that has external lead-out terminals connected respectively to the anode foil and the cathode foil, and a flexible casing that houses the capacitor element and is hermetically sealed, said method comprising the steps of encasing the capacitor element in the flexible casing and applying aging treatment before hermetically sealing the casing, and hermetically sealing the flexible casing, and also relates to a flat aluminum electrolytic capacitor comprising a separator impregnated with the electrolytic solution, the anode foil and the cathode foil, the flat capacitor element that has the external lead-out terminals connected respectively to the anode foil and the cathode foil, and the flexible casing that houses the capacitor element and is hermetically sealed, wherein the electrolytic capacit

Abstract: A ferroelectric capacitor having a ferroelectric film is formed on a conductive silicon substrate. The dielectric capacitor is covered with a first diffusion barrier film, and a second interlayer insulating film is formed on the first diffusion barrier film. A first metal wiring is formed on the second interlayer insulating film, and the first metal wiring is covered with a first buffer film. A second diffusion barrier film is formed on the first buffer film, and a third interlayer insulating film is formed on the second diffusion barrier film. A second metal wiring is formed on the third interlayer insulating film, and the second metal wiring is covered with a second buffer film. A third diffusion barrier film is formed on the second buffer film.

Abstract: Methods and structures for die packages are described. The die package includes an integrated circuit die connected to and elevated above a substrate. In an embodiment, wire bonds connects pads on the die to pads on the substrate. The substrate pads are closely adjacent the die due to the die support being positioned inwardly of the peripheral surface of the die. In an embodiment, the die support includes a paste that flows outwardly when connecting the die to the substrate. The outward paste flow extends from beneath the die support but does not extend outwardly of the die so as to not interfere or contact the substrate pads.

Abstract: A colorless light approaching that of white light in nature, is produced by using a blue color LEDs and a green color LED are covered with a red color phosphorescent glue and a yellow phosphorescent glue in separate layers or a mixed layer.

Abstract: There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.

Abstract: An apparatus in which a device electrode pad in an electronic device and a connecting conductor pattern in a substrate are connected to each other through a plurality of wire thin lines which differ from one another in mechanical characteristic frequencies. Even if the frequency of vibration applied to the apparatus from the exterior coincides with the characteristic frequency of the given wire thin line so that the wire thin line is broken, it does not coincide with the characteristic frequency of the other wire thin line. Accordingly, no resonance phenomenon occurs in the other wire thin line, thereby reducing a probability that the wire thin line is broken.

Abstract: A semiconductor device comprises a semiconductor substrate having a main surface; a semiconductor layer of a first conduction type provided on the main surface of said semiconductor substrate; a first buried layer of the first conduction type provided between said semiconductor layer and said semiconductor substrate; a first connection region of the first conduction type provided around said first buried layer, said first connection region extending from the surface of said semiconductor layer to said first buried layer; a switching element provided in the surface region of said semiconductor layer on said first buried layer; and a low breakdown-voltage element provided in a surface region of said semiconductor layer, said low breakdown-voltage element being closer to said first connection region than said switching element and having lower breakdown voltage than that of said switching element.

Abstract: In accordance with the present invention, there is provided a memory card which is fabricated through the use of a leadframe comprising an outer dambar defining a central opening, and an inner dambar which is disposed within the central opening. The leadframe further includes a plurality of contacts which are disposed within the central opening and attached to the outer dambar. Disposed within the central opening is at least one die pad, with a plurality of conductive traces extending from respective ones of the contacts toward the die pad. At least one tie bar is attached to and extends between the die pad and each of the outer and inner dambars. The tie bar has at least two downsets formed therein such that the die pad, the outer dambar, and the inner dambar extend along respective ones of at least three spaced, generally parallel planes, the plane of the inner dambar being disposed between the planes of the die pad and the outer dambar.

Abstract: A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Abstract: A multi-layer capacitor including a capacitor body including dielectric layers, and first and second internal electrode layers which are alternately laminated by mediation of the dielectric layers. The laminate of the first and second internal electrode layers and the dielectric layers are co-fired. The capacitor body further includes first and second electrode terminals formed on one main surface of the capacitor body. At least a single first via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the first electrode terminal and the first internal electrode layers, and at least a single second via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the second electrode terminal and the second internal electrode layers. The via electrodes have an aspect ratio of 4 to 30 as measured after firing.

Abstract: A substrate and a method for fabricating variable quality substrate materials are provided. The method comprises: selecting a first mask having a first mask pattern; projecting a laser beam through the first mask to anneal a first area of semiconductor substrate; creating a first condition in the first area of the semiconductor film; selecting a second mask having a second mask pattern; projecting the laser beam through the second mask to anneal a second area of the semiconductor film; and, creating a second condition in the second area of the semiconductor film, different than the first condition. More specifically, when the substrate material is silicon, the first and second conditions concern the creation of crystalline material with a quantitative measure of lattice mismatch between adjacent crystal domains. For example, the lattice mismatch between adjacent crystal domains can be measured as a number of high-angle grain boundaries per area.

Abstract: Various embodiments provide a decoder for a memory array, comprising an array of address and output lines, vertical pillars, vertical floating gate transistors, and buried source lines. Each pillar includes single crystalline first and second contact layers separated by an oxide layer. Each floating gate transistor is formed in a single crystalline layer, having a thickness less than 10 nanometers, selectively disposed on a side of one of the pillars. Each transistor includes first and second source/drain regions in contact with the first and second contact layers, respectively, a body region opposing the oxide layer and contacting the first and second source/drain regions, and a floating gate opposing the body region. The source lines are disposed below the pillars and interconnect the first contact layer of pillars. Each of the address lines is disposed between rows of pillars and serves as a control gate.

Abstract: A thin film made of silicon or another IV-group crystals (crystals and mixed crystals of C, Ge, Sn, and Pb) is twice scanned with a laser beam moving in two lateral directions in which crystal grains grow larger in order to form high-quality polycrystals in exact positions in the thin film, while defects uncontrollable by the prior arts are being reduced significantly, to realize a high-quality TFT device. The laser-scanning directions are defined by the crystallization face orientations.

Abstract: A liquid crystal display panel having a display region and a non-display region is provided. The non-display region of the liquid crystal panel comprises a plurality of driver chip joining regions and a plurality of flexible printed circuit bonding regions. There are several groups of circuit lines connecting various driver chip joining regions and flexible printed circuit bonding regions. The ends of the circuit lines connected to the driver chip joining region are the input terminals. Furthermore, each group of circuit lines has a plurality of sub-lines for controlling the pixels of different colors. Among the sub-lines of neighboring circuit lines, the sub-lines at the input terminal for controlling identical color pixels are set up in pairs adjacent to each other. Hence, the resistance-capacitance loading of the liquid crystal display panel is raised and the image quality is improved without incurring greater manpower or manufacturing cost.

Abstract: The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.

Abstract: A structure which ensures against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 ?, serves a sacrificial purpose and prevents damage to an underlying silicide layer by blocking interaction between any fluorine and the underlying silicide that is released when the refractory material is formed.

Abstract: An increased number of fuses per area are provided in this semiconductor device while complying with the predetermined distance between the fuses. The device having a first patterned, conductive interconnect plane on a passivated substrate; a second patterned, conductive interconnect plane on the first patterned, conductive passivated interconnect plane; contact devices for selectively electrically contact-connecting the patterned, conductive interconnect planes to one another; a fuse device in a nonpassivated section of the second patterned, conductive interconnect plane with predetermined fuse regions for selectively linking interconnects; the fuse device being divided into fuse modules with fuse pairs and the fuse regions thereof at a predetermined distance from one another, which can be linked to a predetermined potential via a central interconnect.

Abstract: A transistor (10) is formed as a matrix of transistor cells (13) that have drain metal strips (50) for contacting drains (15) of the transistor cells and source metal strips (55) for contacting sources (35) of the transistor cells. An interconnect layer (1030) overlying the matrix of transistor cells has first portions (201) that contact one the drain metal strips with first and second vias (79) and second portions (101) that contact one of the source metal strips with third and fourth vias (78).