Patents Examined by Louie Wai-Sing
  • Patent number: 7605902
    Abstract: There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 ?m or less, a height H is 0.5 ?m to 10 ?m, a diameter is 20 ?m or less, and an angle ? is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering of light leakage due to orientation disturbance.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: October 20, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Yuugo Goto, Yuko Kobayashi, Shunpei Yamazaki
  • Patent number: 7456480
    Abstract: A semiconductor device includes an input terminal, a first aging device whose source is connected to the input terminal to turn on at ?1 and turn off at ?2 (>?1), a second aging device whose source is connected to the input terminal, whose gate is connected to the drain of the first aging device, and whose drain is connected to the gate of the first aging device to turn on at ?3 and turn off at ?4 (>?3), a first switch whose one terminal is connected to the drain of the first aging device to turn off when the second aging device is on, a second switch whose one terminal is connected to the drain of the second aging device to turn off when the first aging device is on, and an output terminal connected to the other terminals of the first and second switch elements.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: November 25, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Watanabe
  • Patent number: 7436007
    Abstract: A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be adjacent to the first and second patterns. The fifth pattern is arranged between the first and second grid lines to interconnect the first to fourth patterns. A dimension of the fifth pattern in a direction of extension of a plurality of grid lines is set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of the grid lines to an interval of the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns to an interval of the both patterns.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: October 14, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Fujii, Toshiki Morimoto
  • Patent number: 7374993
    Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Matthew W. Miller, Cem Basceri