Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.
Abstract: A lead-frame for connecting and supporting an integrated circuit having an apertured frame with dimensions smaller than the corresponding dimensions of the chip so that chip-pad shoulder can be eliminated and the chip attach fillet is made remote from the chip corner.
Type:
Grant
Filed:
February 7, 2000
Date of Patent:
September 16, 2003
Assignee:
Institute of Microelectronics
Inventors:
Tai Chong Chai, Thiam Beng Lim, Yong Chua Teo, James Tan, Raymundo Camenforte, Eric Neo, Daniel Yap