Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.

Abstract: To improve the radiation property without inhibiting miniaturization of the device, heat generated at a heat generating layer (5) is radiated to a substrate (1) via plugs (7, 17), wiring layers (8, 18), and plugs (9, 19). A cross sectional along the principal plane of the substrate (1) of the plugs (7, 9, 17, 19) is set to be a rectangle, and the long sides of the rectangle are parallel to the direction perpendicular to the direction connecting one end and the other end of the heat generating layer (5). Between the plugs (9, 19) and the semiconductor layer (2) is interposed n-type semiconductor layers (3, 13).

Abstract: A method for manufacturing a semiconductor chip package includes: preparing a semiconductor chip having center and edge bonding pads and a substrate, which includes a first window, a second window, connection pads, external terminal pads, and a wiring pattern; attaching the semiconductor chip on the substrate such that the first window exposes the center bonding pads and the second window exposes the edge bonding pads; connecting the first and second bonding pads to corresponding connection pads; encapsulating side surfaces of the semiconductor chip, a portion of the bottom surface of the substrate, the bonding wires, and the connection pads; and forming external terminals on the external terminal pads of the substrate. The encapsulating includes a first encapsulation of the side surfaces of the semiconductor chip and a portion of the bottom surface of the substrate and a second encapsulation of the bonding wires and the connection pads.

Abstract: Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate and establishing an electrical connection between the bond pad and the terminal.

Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.

Abstract: A vertically mountable semiconductor device including a plurality of bond pads disposed proximate to a single edge thereof. The bond pads are bumped with an electrically conductive material. The semiconductor device may also include a support member. Alternatively, the semiconductor device may be laminated to one or more adjacent semiconductor devices. The present invention also includes a method of attaching the semiconductor device to a carrier substrate. Preferably, solder paste is applied to terminals on the carrier substrate. The semiconductor device is oriented vertically over the carrier substrate, such that the bumped bond pads align with their corresponding terminals. The bumps are placed into contact with the solder paste. The bumps and solder paste are then fused to form a joint between each of the bond pads and its respective terminal, establishing an electrically conductive connection therebetween and imparting structural stability to the semiconductor device.

Abstract: A thin integrated circuit package having an optically transparent window provides a small profile optical integrated circuit assembly for use in digital cameras, video cellular telephones and other devices requiring a small physical size and optical integrated circuit technology. A tape having a conductive metal layer on a surface is used to interface the optical integrated circuit die with electrical interconnects disposed on a surface of the tape opposite the die. A supporting structure surrounds the die and a glass cover is either bonded to the top of the supporting structure over the die, or the glass cover is bonded to the top of the die and the gap between the glass cover and supporting structure filled with encapsulant. The resulting assembly yields a very thin optical integrated circuit package.

Abstract: A 150 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 150 degree bump placement structures is provided.

Abstract: A method of forming a silicate dielectric having superior electrical properties comprising forming a metal oxide layer on a Si-containing semiconductor material and reacting the metal oxide with the underlying Si-containing material in the presence of an oxidizing gas is provided. Semiconductor structures comprising the metal silicate formed over a SiO2 layer are also disclosed herein.

Abstract: A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead from inside to outside being divided into a first inner portion, a supporting portion, a second inner portion and an outer connecting portion. By bending the leads, the first inner portion, the supporting portion, and the second inner portion are formed on different planes. The first inner portion is sticking to the bottom chip and enables the electrical connection to the bottom chip. The supporting portion is sticking to the upper chip, while the second inner portion enables the bonding wires electrically connect the upper chip. This design can pack the upper and the bottom chips with a LOC lead frame without turnover action during wire-bonding.

Abstract: An integrated circuit package device (100, 200, 300) has a plurality of contact points including an inner portion of contact points (120) and an outer portion of contact points (110). The integrated circuit package device includes at least one of the following: (i) one or more power supply contacts (130) configured substantially in said outer portion; (ii) one or more ground contacts (220, 230) configured substantially in said inner portion; (iii) one or more timing or frequency contacts (140) substantially in said outer portion; (iv) one or more data or high speed signal contacts (310) configured substantially in said outer portion of said integrated circuit package device. This provides the advantage that the required capacitors can be located as close to the power supply contacts as possible, and the tracking to these contacts can be kept to a minimum.

Abstract: A semiconductor device formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semiconductor chips have functional elements on their active surface. The first semiconductor chip has, in its active surface, a wiring for connecting the second semiconductor chip and the third semiconductor chip, and a terminal for external connection on its surface opposite to its active surface.

Abstract: A semiconductor device can perform resin sealing of an under-fill region and peripheral portion on the side of a semiconductor chip in the same process step, with shortening periods required for filling and curing the under-fill resin and avoiding formation of an internal void, and can simplify fabrication process and component parts. The semiconductor device includes a through opening provided at a predetermined position of the wired substrate, an under-fill region as a gap portion between the wired substrate and the semiconductor chip, and a molded resin portion as peripheral portion along side edge of the semiconductor chip.

Abstract: An electronic package is provided. The electronic package includes a chip carrier having a first conductive layer which includes at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal. The chip carrier further includes a reference structure having at least two conductive layers such that the signal track is electrically shielded by the reference structure. A semiconductor chip is positioned on the chip carrier and includes at least one terminal electrically interconnected to the at least one contact area.

Abstract: In a two-pole SMT miniature housing in leadframe technique for semiconductor components, a semiconductor chip is mounted on one leadframe part and is contacted to a further leadframe part. The further leadframe part is conducted out of the housing in which the chip is encapsulated as a solder terminal. No trimming or shaping process is required and the housing is tight and is capable of further miniaturization. The solder terminals as punched parts of the leadframe are conducted projecting laterally from the housing sidewalls residing opposite one another at least up to the housing floor which forms the components' mounting surface. The chip mounting surface and the components' mounting surface form a right angle with one another.

Abstract: A semiconductor-chip mounting substrate with a high degree of reliability of an electrical connection between a substrate and a semiconductor chip such as IC chips is provided. The substrate has at least one projection thereon, which is integrally molded with the substrate. A conductive layer is formed on the projection to obtain a first bump. The semiconductor chip has a terminal projecting as a second bump on its surface. The semiconductor chip is mounted on the substrate such that the first bump contacts the second bump. A required contact pressure between the first bump and the second bump is held by use of a pressure holding means.

Abstract: Integrated packages incorporating multilayer ceramic circuit boards mounted on a metal support substrate can be used for temperature control by the metal support substrate. Various electronic components, as well as additional temperature control devices, can be connected to the circuit boards and to the metal support substrate to control or regulate the temperature of operation of the components. The integrated package can be hermetically sealed with a lid.

Abstract: A method of manufacturing a printed circuit board through-hole connection includes forming a through-hole by removing material from the first side of the printed circuit board until the backing and then slightly into the first side of the backing providing a hole. Next, plating through the hole connecting the backing layer, ground layer, and signal layer. Now the plating of the signal layer is removed without removing the connection from the ground layer to the backing. Finally, the hole is filled from the first side of the printed circuit board. A method of manufacturing a MMIC printed circuit board through-hole connection includes forming a through-hole by removing material from the first side of the MMIC printed circuit board through the first signal layer, through the MMIC until the second signal layer, and then slightly into the top side of the second signal layer. Once the material is removed, an electrical connection is provided to the first signal layer, the MMIC and the second signal layer.

Abstract: A semiconductor device is provided, which includes a pair of differential transistors that convert a voltage difference between a first input terminal and a second input terminal into a drain current difference between a first transistor and a second transistor and in which a voltage range of the first input terminal or the second input terminal is wide. A SOI structure MOSFET is used as each of the pair of differential transistors. The MOSFET includes a general MOSFET structure including a source region, a drain region, a well region between both the regions, a gate oxide film on an upper surface of the well region, and a gate electrode on the gate oxide film, and further includes a first conductivity type substrate region under the source region, the drain region and the well region through a buried oxide film.