Abstract: An anisotropic stress buffer includes a plate or sheet-like body having relatively low elastic modulus. A plurality of elements, each having relatively high elastic modulus, are contained in the plate or sheet-like body, in such a manner that the buffer has a characteristic as a high elastic modulus member having a Young's modulus higher than a predetermined value with respect to a compression stress in the thickness direction and also has a characteristic as a low elastic modulus member having a Young's modulus lower than the predetermined value with respect to a tension stress in the planar direction. A semiconductor device includes such a anisotropic stress buffer to which a semiconductor chip is adhered. Electrode terminals of the chip are electrically connected to a wiring pattern formed on the anisotropic stress buffer.

Abstract: A field insulating film defines a plurality of active regions disposed regularly in terms of two dimension on the surface of a semiconductor substrate. Each active region includes one bit contact region and subsidiary active regions extending from the bit contact region in four directions. A plurality of first word lines are formed which extend as a whole in a first direction on the semiconductor substrate, and a plurality of second word lines are formed which extend as a whole in a second direction on the semiconductor substrate, crossing the first word lines. Two subsidiary active regions cross the first word lines and remaining two subsidiary active regions cross the second word lines. A plurality of bit lines are formed which extend as a whole in the first and second directions on the semiconductor substrate, crossing each other. Each bit contact region is connected to a corresponding one of the bit lines. Four transistors share one bit contact, and these four transistors have different word lines.

Abstract: A semiconductor package of this invention has an insulating substrates, wiring layers disposed on the surface of the insulating substrate, a semiconductor chip disposed in a device hole provided in the insulating substrate, inner-joint-conductors for connecting at least part of the bonding pads on the surface of the semiconductor chip to the corresponding inner-joint-conductors and connection lands connected to the wiring layers. The device hole is provided so that it goes through the center of the insulating substrate. The semiconductor chip is thinner than the insulating substrate. Then, this semiconductor chip is disposed in the device hole such that a bottom thereof is flush with a bottom plane of the insulating substrate. Further, this invention provides a MCM in which plural pieces of the thin semiconductor packages are laminated. In the MCM, the semiconductor packages are laminated such that top and bottom faces of the thin silicon chip are inverted.

Abstract: A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.

Abstract: A method and apparatus for fabricating small form factor semiconductor chips having high temperature resistance, good humidity and chemical resistance and good dielectric properties. The semiconductor chip includes a lead frame (10) attached to an integrated circuit die (30) by a lead-on-chip (LOC) method. Wire bonds (40) are employed to connect the integrated circuit die (30) to conduction leads (75) on the lead frame (10). After the wire bonding process, the surface of the wire bonded integrated circuit is encapsulated with a layer of resin (50) using either a direct dispensing method or by a screen printing method. The encapsulated integrated circuit may then be cured and functionally tested.

Abstract: An electronic device is provided comprising a stacked integrated circuit chip assembly wherein the top chip of the assembly is solder connected to the surface of an interconnection substrate with the other chips of the assembly being enclosed in a cavity in the interconnection substrate wherein the cavity and electrical connections of the assembly and between the substrate and top chip are sealed by supplying an encapsulant to the cavity through a through opening in the substrate which communicates with the cavity.

Abstract: An interlayer insulation film is formed on a semiconductor substrate. A wiring is formed on a part of the surface area of the interlayer insulation film. This wiring has a laminated structure including two or more layers. That is, the wiring includes an underlayer or a first conductive layer which is made of Ta in an a phase, and an overlayer or a second conductive layer which is made of an Al alloy.

Abstract: Second electrode pads are formed in a circuit forming region in a surface of a semiconductor chip so as to be electrically connected to first electrode pads formed in an electrode pad region, respectively. The surface of the semiconductor chip is coated with a sealing resin layer and second bumps are formed on the surface of the sealing resin layer so as to be electrically connected to the second electrode pads, respectively.

Abstract: An oxide film 26 is formed on a silicon substrate 10. The oxide film 26 is topped with wiring patterns 34. Top and side portions of the wiring patterns 34 are covered with nitride film top walls 36 and nitride film side walls 38. After an interlayer oxide film 40 is deposited, contact holes 42 are formed through self-alignment. Under the nitride film side walls 38, isotropic etching is carried out to retract side edge surfaces 32 of the oxide film 26 from the wall surface. Contacts 44 are then formed inside the contact holes 42 whose bottom diameter is expanded by the isotropic etching above.

Abstract: An object is to obtain long-term reliability of an electric connection in a power semiconductor module. In a power semiconductor module, the main circuit interconnection directly connected to a power semiconductor chip (3) is formed of a busbar (6) and the power semiconductor chip (3) and the busbar electrode (6a) of the busbar (6) are electrically connected through a conductive resin (12). A member (13) having lower thermal expansion than the busbar electrode (6a) is joined to the busbar electrode (6a) in the part adjacent to said power semiconductor chip (3).

Abstract: An IC module has one or more integrated circuits and a package surrounding them. The IC module is distinguished by one or more additional electronic components being accommodated inside the package, in the immediate vicinity of the integrated circuit.

Abstract: A massive heat slug in thermally coupled to the top of an IGBT to act as a local thermal inertia element to absorb and store heat from the die during peak temperature rise and to return heat to the die at reduced die temperature, thereby reducing the ratio of die peak temperature to die average temperature. The device is useful in applications in which the IGBT is called upon to carry current at a range of frequencies which includes very low (eg 3 Hz) frequencies as in a motor control circuit.

Abstract: A circuit assembly includes a substrate layer, a first conductive layer mounted to the substrate layer and a second conductive layer. The first and second conductive layers are adhered by an adhesive layer having non-electrically conductive particles for separating the first and second conductive layers.

Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Abstract: The microwave hybrid integrated circuit, is providing having a dielectric board (1) provided with a topological metallization pattern (2) and a number of recesses (3) in which semiconductor chips (5) are fixed with a binder (4). The face surface of the chips (5) provided with contact pads (6) are coplanar with the surface of the board (1), and the contact pads (6) of the chips (5) are electrically connected to the topological metallization pattern (2). The walls of the recesses (3) are inclined towards the plane of the board (1) at an angle (&agr;) of 90.1 to 150°.

Abstract: A semiconductor device excellent in bonding strength of bumps with respective protruded electrodes and having high reliability wherein a wiring pattern 28 to be connected to an electrode 22 of a semiconductor chip 20 is formed on an insulting film 23 formed on the semiconductor chip 20 in which the electrode 20 is formed, protruded electrodes 32 are formed on the wiring pattern 28, the wiring pattern 28 is covered with a protective film 36, and a bump 38 for external connection is formed on the end portion of each of the protruded electrodes 32 exposed from the protective film 36, the bump 38 is formed in such a manner that the bump is bonded to the at least entire end face of each of the protruded electrodes 32.

Abstract: A semiconductor package and method for fabricating same is provided that includes a printed circuit board having an electrical circuit formed therein, a plurality of semiconductor chips vertically attached at fixed intervals to the printed circuit board and conductive connecting members that couple bonding pads on each semiconductor chip to pads on the printed circuit board. An encapsulation body encapsulates the semiconductor chips and the conductive connecting members above the printed circuit board. External connection terminals can be attached on a lower side of the printed circuit board for electrical connection to the semiconductor chips through the electrical circuit in the printed circuit board. The semiconductor package and method has increased mechanical and electrical reliability. The semiconductor package is preferably an ultra high density integrated circuit semiconductor package.

Abstract: A semiconductor device is provided in the form of a chip carrier (e.g., chip/IC scale carrier for RF applications) that includes an integrated circuit chip attached to a die attach pad. The device has an interconnect substrate having an upper surface and a lower surface, with a plurality of vias passing through the thickness of the interconnect substrate from the upper surface to the lower surface. The die attach pad is located on the upper surface of the interconnect substrate, and a heat spreader is located on the lower surface of the interconnect substrate. A first group of vias is positioned to intersect both the die attach pad and the heat spreader. A second group of vias is positioned away from the die attach pad and the heat spreader. The upper surface has a plurality of bond pads that are abutting the second group of vias and the lower surface has a plurality of lands that are also abutting the second group of vias.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: A semiconductor device is disclosed wherein a pair of radiating terminals and a plurality of lead terminals are formed from a single lead frame. A hole or holes in each radiating terminal are formed with an equal width and in an equal pitch to those of gaps between the lead terminals, and the opposite sides of each hole of the radiating terminal are connected to each other by a support element. The support elements of the radiating terminals and support elements which interconnect the lead terminals are formed with an equal length and in an equal pitch to allow the support elements to be cut away by a plurality of punches which are arranged in an equal pitch and have an equal width.