Patents Examined by Lourdes (Elle) Cruz
  • Patent number: 6791185
    Abstract: The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Alan G. Wood, Warren M. Farnworth
  • Patent number: 6791194
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: September 14, 2004
    Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 6787926
    Abstract: A microelectronic assembly, and method of making the same, including a wire stitch bonded on an electroplated gold bump or electroless nickel/gold bump on a bond pad of an integrated circuit chip. The electroplated gold bump or electroless nickel/gold bump provides a relatively flat upper surface which is excellent for making a wire stitch bond thereto. The microelectronic assembly may include a multiple integrated circuit chip stack attached to a substrate such as a ball grid array. The electroplated gold bumps or electroless nickel/gold bumps may be formed on all of the integrated circuit chips and wire stitch bonds formed on the electroplated gold bumps or electroless nickel/gold bumps thereby connecting the integrated circuit chips to each other or to an underlying ball grid array.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: September 7, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chih-Chiang Chen, Pei-Haw Tsao, Chung-Yu Wang
  • Patent number: 6787897
    Abstract: A gasket encloses a hermetically sealed environment between a cap wafer and a base wafer. The gasket is bonded to the base wafer using bonding material. The bonding material can be one or more of many substances that exhibit acceptable adhesion, sealing, and other properties that ensure a hermetically sealed environment. The gasket is carved out from the cap wafer material itself. The cap wafer is typically made of extremely strong and rigid material such as silicon. Since the gasket is made from the cap wafer, the gasket itself is also extremely strong and rigid.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: September 7, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Frank S Geefay, Qing Gan, Ann Mattos, Domingo A Figueredo
  • Patent number: 6770980
    Abstract: First electrodes disposed on the surface of the substrate comprise a plurality of chip select electrodes, and the first chip select electrode among a plurality of chip select electrodes to in electrically connected only to a semiconductor element. The N-th (N is a integer of 2 or more) chip select electrode is electrically connected only to the second electrode disposed on the back at position corresponding to the (N−1)-th chip select electrode, and the plurality of chip select electrodes are sporadically disposed in the first electrodes.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Jun Shibata