Abstract: Provided is a memory device and a method of operating the same. The memory device includes a memory block including a plurality of memory cells, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a page buffer group configured to apply the erase voltage to bit lines of the memory block during the erase operation, a voltage generating circuit configured to generate a select line voltage that is applied to a select line of the memory block during the erase operation, and control logic configured to control the source line driver, the page buffer group, and the voltage generating circuit to perform a suspend operation including suspending the erase operation in response to a suspend command.

Abstract: The present disclosure provides a data read circuit and a storage device thereof. The data read circuit includes: a first data transmission path for transmitting first data; a second data transmission path for transmitting second data; a control circuit for receiving a control signal, a first selection signal, and a second selection signal, and outputting a first output signal and a second output signal; and an output circuit for outputting the first data and the second data based on the first output signal and the second output signal, where the output circuit transmits the first data to a third data transmission path before the second data or transmits the second data to a third data transmission path before the first data.

Abstract: A delay buffer unit and an operating method thereof, a computing device and an operating method thereof. The delay buffer unit includes a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit, an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit; an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit; the delay adjustment sub-unit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal, and the delay adjustment sub-unit includes a memristor and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal.

Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

Abstract: A nonvolatile memory device includes a memory cell array configured to store first and second setting data, a page buffer circuit configured to store data of the memory cell array, and a control logic circuit. The control logic circuit is configured to control a sensing operation based on setting data stored in a setting buffer, perform first sensing of the first setting data stored in the memory cell array in a first sensing scheme, and store the sensed first setting data in the page buffer circuit, dump down the first setting data stored in the page buffer circuit into the setting buffer, and perform second sensing of the second setting data stored in the memory cell array in a second sensing scheme based on the first setting data dumped down into the setting buffer, and store the sensed second setting data in the page buffer circuit.

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

Abstract: A stacked semiconductor device includes at least one upper chip including first and second channels, each including first and second pseudo-channels; and first and second transfer control circuits respectively corresponding to the first and second channels, each configured to select one of the first and second pseudo-channels according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel, and transfer a data word between the selected pseudo-channel and a lower chip, wherein the first transfer control circuit transfers the data word in a first order in units of bytes, and the second transfer control circuit transfers the data word in a second order in units of bytes, opposite to the first order.

Abstract: A memory device may include a reference voltage generator that generates a reference voltage, a voltage regulator that includes a plurality of driving blocks generating an internal voltage based on the reference voltage, and a power line that receives the internal voltage. At least one of the plurality of driving blocks may include a first unit driver that generates a first output current flowing through the power line based on the reference voltage and a change in the internal voltage, and a second unit driver that generates a second output current larger than the first output current flowing through the power line, based on the reference voltage and the change in the internal voltage. The first unit driver may generate the first output current faster than the second output current of the second unit driver.

Abstract: In some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. The memory device may determine that the portion of the memory is associated with a reliability risk. The memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an alternative erase scheme to erase the host data from the portion of the memory, wherein during a first portion of the alternative erase scheme, a first voltage is applied to even word lines and a second voltage, that is different from the first voltage, is applied to odd word lines, and wherein during a second portion of the alternative erase scheme, a third voltage is applied to the even word lines and a fourth voltage is applied to the odd word lines.

Abstract: Provided is a memory semiconductor device in which a p-type semiconductor region is formed at an n+layer to which a bit line is connected, an n-type semiconductor layer to which a source line is connected is further formed, a first gate insulating layer and a first gate conductor layer to which a word line is connected exist, a second gate insulating layer and a second gate conductor layer to which a plate line is connected are provided, and a distance from the n+layer to the first gate conductor layer is smaller than a distance up to the second gate conductor layer. At the time of an erase operation, the plate line and the source line have a positive electric potential of the same polarity or have a voltage of 0 V.

Abstract: In some implementations, a memory device may receive, from a host device, a single-level cell (SLC) program command instructing host data to be written to one or more subblocks of memory. The memory device may determine whether a word line associated with a subblock, of the one or more subblocks, is associated with a reliability risk. The memory device may determine whether to perform a word line leakage monitoring procedure associated with a programming scheme to be used to program the subblock based on whether the word line is associated with the reliability risk.

Abstract: Disclosed are a resistive random access memory (RRAM) structure and operating method. The RRAM structure includes RRAM cells arranged in columns and rows with all cells in a column connected between source and bit lines for the column and with all cells in a row connected to a word line for the row. The RRAM structure also includes peripheral circuitry enabling all memory operations to be performed without selective source line biasing. For example, during a reset operation, the following voltage conditions can be applied: a low positive voltage (e.g., of +1.8V) to the word line of the row containing the selected RRAM cell; a low negative voltage (e.g., of ?1.8V) to all other word lines; and another low negative voltage (e.g., of ?1.6V) to the bit line of the column containing the selected RRAM cell. All source lines and all other bit lines can be discharged to ground.

Abstract: A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.

Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.

Abstract: A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.

Abstract: A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the data stored in the memory. When access circuitry of the memory array begins a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value less than a threshold voltage of transistors. Therefore, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuitry provides the reset data on the write bit lines, and asserts each of the write word lines of the memory array. To complete the write operation, the access circuitry returns the power supply voltage level from below the threshold voltage level to an operating voltage level.

Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

Abstract: A first memory instance comprises one or more first bitcell arrays and one or more peripheral circuits. The first memory instance further comprises a high-speed voltage monitoring circuit operable to monitor a supply voltage and a power down signal in the first memory instance, the high-speed voltage monitoring circuit further operable to provide an output power ready signal derived from the supply voltage and the power down signal such that the output power ready signal indicates when the power down signal is low and the supply voltage is high.

Abstract: A memory device includes a first wiring, a second wiring, a memory cell connected between the first wiring and the second wiring, a first power line, a sense amplifier, a current control circuit provided between the first power line and the sense amplifier and including a control terminal connected to a first node, a capacitance element provided between the first node and the second wiring and including a first terminal electrically connected to the second wiring and a second terminal connected to the first node, a second power line, and a first element having an electrical resistance provided between the first node and the second power line.

Abstract: The memory device includes an array of memory cells that are arranged in word lines and are programmed to contain data. Circuitry is configured to erase the memory cells of the memory block in an erase operation. During erase, the circuitry is configured to begin an erase operation to erase the memory cells and suspend the erase operation for a first suspension. After the first suspension is completed, the circuitry is configured to resume the erase operation. The circuitry is then configured to receive an instruction to suspend the erase operation for a second suspension and dynamically determine a minimum resume latency based on a vulnerability of the memory block to erase errors. Only after the minimum resume latency has passed following the step of resuming the erase operation after the first suspension is completed, the circuitry is configured to suspend the erase operation for the second suspension.