Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation is regions are formed over a semiconductive substrate.

Abstract: A method of making a metal-insulator-metal (MIM) capacitor (158) having self-passivating plates (143, 155). A liner (116) is deposited on a workpiece (112) and dielectric (114). A conductive layer (142) is deposited and annealed to form dopant-rich region (144). Insulating region (145) is formed on exposed portions of dopant-rich region (144) by exposure to atmosphere or oxygen. Capacitor dielectric layer (146) is disposed over the first capacitive plate (143). A second capacitive plate (155) is formed over the first capacitive plate (143) and capacitor dielectric layer (146). The second capacitive plate (155) is annealed to form dopant-rich region (154) and exposed to atmosphere or oxygen to form insulating region (156). Optional seed layer (140) may be deposited prior to the formation of the first capacitive plate (143).

Abstract: A method is disclosed to improve copper barrier and adhesion properties of copper interconnections in integrated circuits. It is shown that combining ion metal plasma (IMP) deposition along with in-situ chemical vapor deposition (CVD) of barrier and adhesion materials provides the desired adhesion of and barrier to diffusion of copper in damascene structures. IMP deposition is performed with tantalum or tantalum nitride while CVD deposition is performed with a binary or a ternary compound from a group consisting of titanium nitride, tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, titanium silicon nitride. IMP deposition provides good adhesion of copper to insulator materials, while CVD deposition provides good sidewall coverage in a copper filled trench and a copper seed layer provides good adhesion of bulk copper to adhesion/barrier layer. The IMP/CVD deposited adhesion/barrier layer is thin, thus providing low via resistance.

Abstract: The present invention relates to a method of manufacturing a junction in a semiconductor device. When forming an elevated source/drain junction (ESD) of a buried channel field effect transistor (BC-FET) using a selective epitaxial growth (SEG) technique, a self-aligned epitaxial silicon (SESS) is formed on the lower portion of a gate side-wall spacer, resulting in the improvement of a short channel characteristic by suppressing a facet occurred when forming an elevated source/drain junction (EDS) of the buried channel field effect transistors (BC-FETs) using a selective epitaxial growth (SEG) technique as well as the increase of the current density by lowering the series resistance of source/drain extension.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques.

Abstract: A method for forming n- and p-type contacts for CMOS integrated circuits is described wherein the contact openings are ion implanted after being etched to provide supplemental doping to the exposed device elements in order to secure a reliable low resistance interface with subsequently deposited contact metallurgy The p-type contact openings and the n-type contact openings are patterned, etched, and ion implanted separately, thereby requiring only two photolithographic steps. By etching and implanting the p-contacts and n-contacts separately, the method eliminates one highly complex and contaminative photolithographic step and introduces a less complex etch step with reduced contamination risk, thereby achieving a cost saving by improving yield and reducing process time. It is optional which contacts are processed first.

Abstract: A method of forming borderless contacts and vias is disclosed. Borders which are conventionally provided in aligning contacts and vias to device and/or metal regions in a semiconductor device take up too much valuable real estate on semiconductor substrates, and hence reduce productivity of the products. By employing a hard-mask of this invention, and a specific sequence of process steps, alignment can be achieved without the need for borders. First, a thin nitride layer is deposited on an insulating layer formed over a substructure of a substrate having device and/or metal regions. The hard-mask is patterned with metal line openings, and a photoresist layer is formed with contact or via pattern over the already patterned hard-mask. The contact/via openings are etched into the dielectric layer until the substructure is reached. The hole openings are filled plug metal and then partially etched back, leaving a plug in the hole opening.

Abstract: Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive modules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

Abstract: An improved process for forming blanket planarization of the multilevel interconnection of a semiconductor substrate by LPD-SiO.sub.2 (Liquid-Phase Deposition) selective deposition technique which LPD-SiO.sub.2 is not deposited on silicon nitride, and forming silicon dioxide to achieve blanket planarization of multilevel interconnection.

Abstract: A method of fabricating a lightly doped drain thin-film transistor having an inverted staggered structure is disclosed. The transistor has a glass substrate and a gate formed by a Cr layer on the substrate. An insulating layer and a semiconductor layer are deposited on the substrate and the gate. A first photo-resist layer is coated on top of the semiconductor layer. Back-side exposure and self-aligned technique are used to form an unexposed area slightly smaller than the gate area with high energy light. Low energy ion implantation is then performed on the exposed semiconductor layer to produce the lightly doped region. After removing the first photo-resist layer, another photo-resist process including a second photo-resist coating, back-side exposure and self-aligned technique is performed to form an unexposed area slightly larger than the gate area with low energy light. High energy ion implantation is then performed on the exposed semiconductor layer.

Abstract: A method of depositing a material upon a substrate is disclosed. A material, such as photoresist, is deposited upon a substrate such as a semiconductor wafer by spinning the substrate and commencing deposition at the edge of the wafer and moving inward in a spiral pattern. The method produces a more uniform coating than hitherto available.

Abstract: An improved process and integrated-circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate and a NMOS electro static discharge circuit formed in a P well on the substrate. The improvement includes an electro static discharge NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped polysilicon gate electrode of the electro static discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.

Abstract: A method of manufacturing an interlayer dielectric for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 .mu.m or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC.sub.2 H.sub.5).sub.4 and O.sub.2 at approximately 9 torr between 370.degree. C. to 400.degree. C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.

Abstract: In a method for forming a metal wiring layer of a semiconductor device an insulating layer is formed on a semiconductor substrate having impurity-doped regions. A contact hole is formed in the insulating layer to expose an impurity-doped semiconductor region. Thereafter, a diffusion barrier layer is formed on the inner surface of the contact holes and on the surface of the semiconductor substrate exposed by the contact holes. The diffusion barrier layer is heat-treated for two minutes to one hour in a vacuum at a temperature of 450.degree. C. to 650.degree. C. Then, a metal wiring layer of a semiconductor device is formed on the diffusion barrier layer.

Abstract: A method is disclosed for making a thin film capacitive memory device with a high dielectric constant. A lower electrode of yttrium or hafnium is formed on a semiconductor substrate. A dielectric insulating film is formed on the lower electrode, and the dielectric insulating film is annealed such that at thinner portions the dielectric insulating film, the lower electrode is oxidized more heavily than at thicker portions of the dielectric insulating film. An upper electrode is formed on the dielectric insulating film.

Abstract: A silicon dioxide film and a silicon nitride film are sequentially deposited on an n-type silicon substrate in this order. After the silicon nitride film is selectively removed to form openings, an impurity (boron) for forming a channel stopper is diagonally implanted through the resultant openings. In this case, the direction of the ion implantation, which is projected in a plane perpendicular to the direction of the channel length of a FET in a memory cell region, is 45.degree. tilted with respect to the direction of the normal of the surface substrate, so that implanted boron reaches the end portion of the channel region. Thereafter, LOCOS films are formed and, simultaneously, an impurity (boron) for threshold adjustment is implanted into the respective FET formation regions of the memory cell region and of a peripheral circuit region.