Abstract: A method and substrate structure for fabricating highly conductive components on microelectronic devices. In one embodiment in accordance with the principles of the present invention, a first dielectric layer is formed over a base layer of a substrate, a second dielectric layer is deposited onto the first dielectric layer, and a third dielectric layer is deposited onto the second dielectric layer. The first, second and third dielectric layers define a dielectric stratum in which the first and second dielectric layers may be selectively etchable from one another so that the second dielectric layer etches at a faster rate than the first layer in the presence of a selective etchant. After the dielectric layers are deposited onto the substrate, a void is etched through the second and third dielectric layers.

Abstract: A method of doping metal layers on integrated circuits to provide electromigration resistance and integrated circuits having metal alloy interconnects characterized by being resistant to electromigration are provided. The process consists of the steps of (1) depositing a film of a pure first conductive metal upon a semiconductor, (2) patterning and etching the deposited film, (3) subjecting the patterned conductive metal film to metallo-organic chemical vapor deposition in order to deposit upon the first deposited metal and not upon any semiconductive areas present in the patterned conductive metal film a doping amount of a second conductive metal different from the first metal, and (4) heating at a temperature sufficient to uniformly diffuse the second metal through the bulk of the patterned first conductive metal film.