Patents Examined by Lynnne A. Gurley
  • Void forming method for fabricating low dielectric constant dielectric layer
    Patent number: 6165897
    Abstract: A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a microelectronics substrate layer employed within a microelectronics fabrication. There is then formed upon the microelectronics substrate layer a patterned microelectronics layer. There is then formed conformally over the patterned microelectronics layer a conformal silicon oxide dielectric layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing silane as a silicon source material.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: December 26, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Syun-Ming Jang