Patents Examined by M. Banankhah
  • Patent number: 5454107
    Abstract: A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: September 26, 1995
    Assignee: VLSI Technologies
    Inventors: Judson A. Lehman, Mike Nakahara, Nicholas J. Richardson