Abstract: An interconnect includes a pad and at least two vias coupled to the pad. In one embodiment, the pad has five substantially straight edges, one via directly coupled to the pad by being formed substantially beneath the pad, and one via coupled to one of the five substantially straight edges by a tapered conductive segment. In another embodiment, the pad has three vias directly coupled to the pad and formed substantially beneath the pad. A method of forming an interconnect includes forming at least two vias in a substrate and coupling a pad to each of the at least two vias.

Abstract: A semiconductor module, comprising a wiring substrate on which wiring is formed, a semiconductor device electrically connected to the wiring formed on the wiring substrate, and an external connection terminal arranged on the semiconductor device mounted side of the wiring substrate so as to be a connected portion between the wiring and the outside electrically connected thereto, wherein there is formed an insulating resin layer thicker than the semiconductor device between the wiring substrate and the external connection terminal.

Abstract: A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging, circuit card, electronic device, and a computer system. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: Stabilizers for placement on a surface of a semiconductor device component and methods for fabricating and placing the stabilizers on semiconductor device components. Upon assembly of the semiconductor device component face down upon a higher level substrate and joining conductive structures between the contact pads of the semiconductor device component and corresponding contact pads of the higher level substrate, the stabilizers at least partially stabilize the semiconductor device component on the higher level substrate to prevent tilting or tipping of the semiconductor device component relative to the higher level substrate. The stabilizers can also be positioned and configured to define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate. The stabilizers may be either preformed structures or formed on the surface of the semiconductor device component. A stereolithographic method of fabricating the stabilizers is disclosed.

Abstract: Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to form a recess. An array of electrical connection pads is located within the recess. A semiconductor die can be flip chip attached to the interposer by at least partial insertion of the semiconductor die within the recess with discrete conductive elements between bond pads of the semiconductor die and electrical connection pads of the interposer. The electrical connection pads communicate with a number of other electrical contact pads accessible elsewhere on the interposer, preferably on a lower surface thereof. A low viscosity underfill encapsulant is disposed between the semiconductor die and the interposer and around the discrete conductive elements by permitting the same to flow into the space between the die and the perimeter wall.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: A reliable microchip controller board and a manufacturing method thereof suitable for mass production are provided. A board wherein a programmable microchip controller is mounted includes; terminals for writing a program into the microchip controller and a circuit pattern connecting an operating terminal to shared terminals which are disconnected. A non-programmed microchip controller is mounted on the board in a state where patterns are disconnected and then programmed. The disconnected portion is connected thereafter.

Abstract: A multilayer ceramic carrier for an optical element includes a terraced cavity for retaining a vertically receiving or vertically emitting optical element. The multilayer ceramic carrier includes conductive traces interposed between the ceramic layers and which extend into the terraced cavity along the trenches formed in the cavity. A vertical cavity surface emitting laser or vertically receiving optical element is wire bonded to the conductive traces which extend into the cavity. In one embodiment, the terraced cavity of the multilayer ceramic carrier includes a VCSEL and photodetector therein, the photodetector capable of monitoring the output optical power of the VCSEL. The method for forming the multilayer ceramic carrier includes forming a plurality of layers of ceramic tape, joining the layers, then co-firing the stacked layers. The multilayer ceramic carrier is joined to a plastic optical housing which includes an aperture for securing an optical fiber.

Abstract: A method is provided for reconstructing an integrated circuit package comprising: attaching a die to exposed wire bond pads of a lead frame so that the die is electrically connected to the lead frame; and encapsulating the die and the wire bond pads in an encapsulant; and reshaping an upper surface of the encapsulant where at least a portion of the encapsulant reshaping is performed by a lapping process.

Abstract: A II-VI semiconductor device includes a stack of II-VI semiconductor layers electrically connected to a top electrical contact. A GaAs substrate is provided which supports the stack of II-VI semiconductor layers and is positioned opposite to the top electrical contacts. A BeTe buffer layer is provided between the GaAs substrate and the stack of II-VI semiconductor layers. The BeTe buffer layer reduces stacking fault defects at the interface between the GaAs substrate and the stack of II-VI semiconductor layers.

Abstract: A sensing element is formed on a silicon (Si) substrate and covered with a cap. The cap has a leg portion having a titanium layer and a gold layer formed in that order on the lower surface thereof. The silicon substrate has an Si bonding frame at a position corresponding to the leg portion. When bonding the Si bonding frame of the silicon substrate and the leg portion of the cap, the titanium layer deoxidizes a naturally oxidized silicon layer formed on the Si bonding frame, whereby the silicon substrate and the cap can be uniformly bonded together with an Au/Si eutectic portion interposed therebetween. In this case, the Au/Si eutectic portion includes a titanium oxide accompanying the deoxidization of the naturally oxidized silicon layer.