Abstract: The present invention is a method and apparatus for tracking a state of a page of a memory device which has at least a dependent bank structure. A page entry table contains attribute entries of the page. An access control circuit generates access information and a command in response to a memory access. A tracking circuit is coupled to the page entry table and the access control circuit to update the attribute entries in the page entry table according to the command and the access information.

Abstract: A data processor controlled user interactive display system for displaying hypertext documents, each including a sequence of display screen pages received at a receiving display station from a communications network such as the World Wide Web. Automatic sizing of the cache for received pages at the receiving display station is provided. This cache includes portions of the station's disk storage means and random access memory means for storing data representative of received screen pages. The size of the portions of disk storage and random access storage means needed for the cache are determined by prior monitoring of the quantities of disk storage and of random access memory used in said cache during prior transmission of screen pages to said receiving display station. The size of portions of disk storage and random access memory allocated to the present cache are based upon said prior monitoring. These sizing functions are most effectively included in a network interactive browser.

Abstract: The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache miss. The prefetch is initiated when it is guaranteed that instructions in the subsequent cache line will be referenced. This occurs when the current instruction is either a non-branch instruction, so instructions will execute sequentially, or if the current instruction is a branch instruction, but the branch forward is sufficiently short. If the current instruction is a branch, but the branch forward is to the next sequential cache line, a prefetch of the next sequential cache line may be performed. In this way, cache miss latencies may be reduced without generating cache pollution due to the prefetch of cache lines which are subsequently unreferenced.

Abstract: The data processing apparatus comprises a cache having a plurality of cache lines for storing data values retrieved from a plurality of memory regions, when a data value from a first memory region is stored in the cache and is subsequently updated within the cache by a new data value, the new data value is not transferred to memory until that new data value is removed from the cache. A marker is associated with each cache line and is settable to indicate that the data values stored in the corresponding cache line are from said first memory region. A protection unit for controlling the transfer of data values between the cache and the memory, is arranged, when said data values are to be loaded from the memory into a cache line of the cache, to determine whether said data values are from said first memory region and to cause the marker to be set accordingly.

Abstract: A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more subarray selection bits in each of the first and second cache addresses, and further preferably includes a common contention logic unit for both the first and second cache access circuits. The first cache address is retained within the first cache access circuit so that the first cache access circuit does not need to re-generate the first cache address. If the same word (or doubleword) is being accessed by multiple load operations, this condition is not considered contention and both operations are allowed to proceed, even though they are in the same subarray of the interleaved cache.

Abstract: A method and system in data processing system are disclosed for the dynamic scheduling of a plurality of requests to access a disk. Each of the requests is associated with a location on the said disk which each of the requests is attempting to access. A scan queue is established for storing the plurality of requests. The plurality of requests are processed in a sequential order. The sequential order is determined utilizing the location on the disk being accessed by each of the requests. Upon one of the stored requests being urgent, the urgent request is processed. The urgent request is associated with a first location on said disk. Processing of the requests then continues in a second sequential order. The second sequential order is determined utilizing the first location. The next request to be processed is one of the requests which is associated with a physically closest location on the disk.

Abstract: An integrated circuit includes trim circuitry to control operations of internal circuitry. The integrated circuit includes multiplex circuitry for coupling the trim circuitry to internal circuits via a trim bus in a manner which reduces die area. The trim circuitry is controlled such that fuses used to control different level and timing parameters are grouped together and routed across the integrated circuit using the trim bus and multiplex circuit.