Abstract: In the decoding of a data stream encoded in a Miller type code the number of intermediate duration transition intervals are counted between successive transition intervals of long duration. Whenever an odd number of intermediate duration transition intervals are detected between successive transition intervals of long duration, an error signal is produced. The error signal is developed by two gates utilizing signals otherwise present in the decoding apparatus.

Abstract: A system for on-line, concurrent self-testing of a computer is disclosed which is capable of checking the "test kernel" of the computer; that is, the portion of the computer that must be fault-free in order for the computer to test itself with a self-test program. The test kernel includes the computer CPU, the ROM which contains the self-test program, and the intraboard data, address and control buses, bus drivers and multiplexers. The system operates in a transparent fashion to test the computer during its normal operation. The system includes a linear feedback shift register connected to control signal outputs of the CPU and thus determines whether the CPU produces the proper control signals during fetch and/or execution of each program instruction.