Patents Examined by M. K. Wambach
  • Programmable logic array having a changeable logic structure
    Patent number: 4876466
    Abstract: Programmable Logic Array PLA) cells are arranged at intersections of input lines and output lines of the array. Particular PLA cells to be programmed are arbitrarily selected by word line and bit line decoders. Switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.
    Type: Grant
    Filed: November 10, 1988
    Date of Patent: October 24, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Harufusa Kondou, Hiroshi Kuranaga
  • Fast CMOS NAND gate circuit
    Patent number: 4851713
    Abstract: An n-input CMOS NAND-gate having n pMOS transistors connected in parallel with their inputs connected to different input terminals and their outputs connected to a common output terminal. First and second sets of n nMOS transistors are each connected in series between the output terminal and ground. The inputs of the first set of nMOS transistors are connected to the input terminals in order, and the inputs of the second set of nMOS transistors are connected to the input terminals in the reverse order.
    Type: Grant
    Filed: March 10, 1988
    Date of Patent: July 25, 1989
    Assignee: GTE Laboratories Incorporated
    Inventor: Sywe-Neng Lee