Abstract: A substrate bias voltage generator circuit has a substrate bias voltage detector circuit, a substrate bias driver circuit, and a charge pump circuit. the substrate bias voltage detector circuit detects a substrate bias voltage applied to a semiconductor substrate and outputs a substrate bias voltage detection signal. The substrate bias detector circuit includes a P-channel transistor with a gate terminal and an N-channel transistor with a substrate terminal, both terminals being connected to the semiconductor substrate and the substrate bias voltage which is a back bias for the N-channel transistor.

Abstract: An output circuit is disclosed for a semiconductor integrated circuit, having a controllable load drive capability. In a training mode for setting a load drive capability, a comparator compares the output signal generated from a driver circuit with the externally designated reference voltage. The control circuit controls the load drive capability of the driver circuit in response to the result of the comparison. The load drive capability of driver circuit 2 is set to a desired value by repeating the processing for these comparison and control. Accordingly, by externally controlling the level of the reference voltage, an output buffer can be obtained which is capable of setting the load drive capability to any value.

Abstract: Disclosed is an arbiter circuit for arbitrating a contention between two request signals which simultaneously attain the H (logical high) level indicating a "request". In this arbiter circuit, buffer circuits, having different input logic threshold voltages, are connected to the respective outputs of two three-input NAND gates. The respective outputs of these two buffer circuits, as signals indicating "acknowledgement" or "negative acknowledgement" of the request signals, are derived as final outputs of the arbiter circuit. One of the buffer circuits has an input logic threshold voltage lower than a logic threshold voltage of the two NAND gates, while the other buffer circuit has an input logic threshold voltage set higher than the logic threshold voltage of the NAND gates.

Abstract: A FET load circuit consists of two depletion-mode FETs connected in series. The gate of one FET is connected to ground. The gate of the other FET is connected to its source. This load circuit reduces power dissipation and provides superior operational stability, particularly in gallium-arsenide DCFL logic and memory circuits.

Abstract: An input buffer for translating TTL level signals to ECL level signals has a level shifter having a first and a second inupt transistor. The first input transistor receives the input signal and the second transistor receives a reference voltage. First and second transistor loads are coupled to the first and second transistors, respectively. Both the first and second loads are biased to the same saturation current. The saturation current is derived from a current source. The reference voltage is set at a voltage which is between the maximum voltage of a logic low of the input signal and the minimum voltage of a high of the input signal. The deferential level shifter develops a voltage differential which is converted to ECL level signals by a differential amplifier.

Abstract: A circuit is disclosed which converts CMOS logic input signals to ECL output signals. A pair of FETs, arranged as a conventional CMOS inverter, responds to the CMOS logic input signals and drives a bipolar transistor operating as a voltage follower. The emitter of the bipolar transistor serves as the output of the buffer providing the ECL output signals. A resistor having a predetermined resistance couples between a voltage source and the base of the bipolar transistor. First one of the pair of FETs couples a constant current source to the resistor and the base of the bipolar transistor when the buffer is supplying an ECL logical "zero" logic signal. The current from the current source passing through the resistor establishes the ECL logical "zero" output voltage. Second one of the pair of FETs shunts the resistor when the buffer is supplying an ECL logical "one" output, allowing faster transitioning of the output of the buffer from an ECL logical "zero" to a logical "one".

Abstract: An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally caused by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors is controlled by controlling the voltage on the gate or base of the transistor which is providing the particular logic state. This control is responsive to the magnitude of the power supply voltage. An impedance which varies in resistance with supply voltage is placed in series between the positive power supply terminal and the gate or base of the output transistors.

Abstract: A power supply voltage level sensing circuit on an integrated circuit generates a reset signal that holds the components of the integrated circuit in a defined state when the power supply voltage level drops below a predetermined voltage. The reset signal is released when the power supply voltage level returns to above the predetermined voltage.The voltage level sensing circuit is comprised of two inverters and a filter circuit. The inverters start to conduct at different power supply voltage levels and have different trigger point characteristics.The power supply voltage level sensing circuit may be coupled with a power-on reset circuit to create a voltage sensing power-on reset circuit which generates a reset signal not only when the power supply voltage is first supplied to the circuit, but also when the power supply voltage level temporarily falls below a selected value.

Abstract: In conventional logic buffer circuits, internal signal overshoot during switching transitions causes power supply spikes or bounce, which may in turn degrade the operational reliability of other circuits in the same system. By using a pair of current amplifier circuits within the logic buffer circuit to shunt a portion of the signal overshoot, the output current of the logic buffer circuit is caused to change linearly with time, so that power supply bounce or spikes are substantially reduced.

Abstract: An improved logic circuit is disclosed, of the type in which one or more input signals, generated by one or more input signal generator circuits, are referenced to a threshold voltage, determined by a threshold voltage generator circuit, to determine whether said one or more input signals are in a high or low state. In this improved logic circuit, the time constants of the input signal generator circuits are matched with those of the threshold voltage generator circuit so that any power supply perturbations commonly applied to the input signal generator circuits and threshold voltage generator circuit, such as due to the switching on or off of output loads, will result in these circuits having substantially identical frequency responses and amplitude versus time responses.

Abstract: Logic gates with large logic swings and large noise margins use complementary pull-up and pull-down enhancement-mode drivers. Connected between the input node of the logic gate and the control electrode of each of the drivers is a series combination of a level shifter (or constant-voltage element) and a current regulator (or constant-current element). The level shifter permits a voltage drop approximately independent of current, while the current regulator limits current flowing between the input node and the control electrode approximately independent of voltage.

Abstract: To reduce the total power dissipation of an emitter-follower driver or logic circuit, an MOS transistor is connected between an output terminal of the circuit and a suitable voltage source. The MOS transistor is operated in opposite phase to an emitter follower bipolar transistor that provides driving current to the output terminal, so that one is on while the other is off. The MOS transistor limits the current in the emitter follower transistor in either state of the circuit, thus reducing power dissipation. It also provides for a larger transient driving current to the output terminal, thus increasing the switching speed of the circuit.

Abstract: A logic level converter circuit has a first state (E.sub.1 low, E.sub.2 low) which produces a high level on the output TTL S, a second state (E.sub.1 high, E.sub.2 low) which produces a low level on the output S, and a third state (E.sub.2 high) which a very high impedance in which the two output transistors T.sub.5 and T.sub.6 are turned off. The current of a current source I.sub.1 is directed by the transistors T.sub.1, T.sub.2, T.sub.7, T.sub.8 and T.sub.9. In the second state and the third state, a diode D.sub.3 which bridges the bases of the transistors T.sub.5 and T.sub.6 (points A and B) is conductive, while a diode D.sub.2, connected between ground and the point A, is conductive in the third state.

Abstract: A decoder incorporates the advantageous features of both bipolar and BICMOS decoding circuits through the use of BIPMOS technology. PMOS gating transistors are used to control the operation of bipolar output transistors. It is only necessary to operate the PMOS transistors with relatively small drain voltage variations, since the bipolar transistors are sensitive to such small variations. Further, transient signals are referenced to one power supply voltage only, to thereby make the logic swing and performance characteristics of the decoder independent of power supply voltage variations. Therefore it becomes possible to use PMOS transistors that have smaller voltage requirements than conventional CMOS circuits.

Abstract: A multi-input logic gate is disclosed having particular application for use as an AND or OR gate in a digital circuit. The OR gate of the present invention includes drive, sense and reference rails. A plurality of input lines are coupled to a gate of a plurality of N-channel transfers disposed between the drive and sense rails, one input line per transistor. The drive rail is coupled to ground through an N-channel transistor whose gate is controlled by the state of a detect line. The sense and reference rails are coupled to a voltage source (V.sub.dd) through P-channel transistors whose gate is also coupled to the detect line. The P-channel transistor coupled to the sense rail is sized to pass more current than the corresponding transfer on the reference rail. A sense amplifier is coupled to the sense and reference rails, and outputs a predetermined signal as a function of the voltage difference of the rails.

Abstract: A TTL compatible buffer circuit responsive to an input signal and having a controlled ramp output is disclosed and includes a low and a high output voltage driver, each driver being comprised of a Darlington pair of transistors, and each driver being separately controlled by its own control circuit. Each control circuit includes at least a capacitor and resistor which are arranged to control the voltage at the base of the upper transistor of the Darlington pair output voltage driver. In this manner, the voltage at the high voltage driver increases in a substantially linear manner when the input signal goes from low to high, and the voltage at the low voltage driver decreases in a substantially linear manner when the input signal goes from high to low. The turn on time of the drivers is thus relatively long. Each control circuit further includes a transistor which permits the respective output voltage driver to turn off quickly.

Abstract: A high speed interstage STL buffer (27) is disclosed having a low threshold and high driving capability. A first Schottky-clamped grounded emitter transistor (28) receives input signals through a Schottky steering diode (38) and inverts the input signal. The input signal is applied in parallel through a Schottky steering diode (20) to a second Schottky-clamped grounded emitter transistor (12). The collector (22) of the second transistor (12) provides an output of the buffer (27) for driving load current in one direction with respect to the buffer output. A third transistor (40) connected as an emitter follower has the emitter (42) thereof connected to the buffer output for driving load currents in the other direction. The base (46) of the emitter follower transistor (40) is coupled by a Schottky steering diode (50) to the collector (32) of the first transistor (28).

Abstract: A fault-tolerant digital integrated circuit includes functionally identical circuit blocks, each of such identical circuit blocks having an input region and an output region. The input regions receive identical input signals and the output regions are electrically connected to a combining logic gate, typically an OR gate. In this way a defect in any one of the identical blocks will not prevent operation of the circuit.

Abstract: In a semicondutor IC device such as a memory device with circuits to be selected and circuits to select one of these circuits to be selected in response to an input signal, each circuit to be selected is divided into parts but a fuse is provided corresponding to each of the parts such that each of the defective parts can be replaced by redundancy circuit without invalidating the other parts of the same circuit that is replaced.

Abstract: The present invention provides circuitry for disabling the output gate of an ECL programmable array logic device so that TTL programming and test signals may be applied to the ECL output node. The disable control circuit is responsive to a control signal to provide pull down current to the ECL output gate. A sensing circuit connected to the ECL output senses the TTL voltage level on the output in the programming mode without disturbing the ECL output in the normal mode.