Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

Abstract: A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. Unique sensing techniques are provided to sense the states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently.

Abstract: The present invention is related to a semiconductor memory device improving refresh performance by reliably generating an internal voltage. The internal voltage generator for use in the semiconductor memory device includes a cell plate voltage generator, a driving voltage generator, and a bit line precharge voltage generator. The bit line precharge voltage generator includes a half driving voltage generator for receiving the driving voltage to thereby generate the bit line precharge voltage, a second reference voltage generator for generating the second reference voltage, and a bit line precharge voltage releasing device for discharging a surplus voltage.

Abstract: A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.

Abstract: A multi-ported register comprises a Global Bit Line (GBL) to couple a gate to a data output line via an output transistor. A Local bit Line (LBL) couples the gate to a first register file cell and a second register file cell, said second register file cell disposed closer to the data output line than the first register file cell. At least one transistor in the first register file cell having a stronger drive current than the at least one transistor in the second register file cell. At least one of, the output transistor, the gate, and the first register file cell of a first bank have a stronger drive current than the corresponding output transistor, the gate and the first register file cell of a second bank said second bank being closer to the data output line.

Abstract: A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay time in the delay time is controlled according to a chip address supplied to these two pads.

Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

Abstract: A semiconductor memory device comprises a driver including a first resistor, and a control signal generator including a second resistor. A storage unit is employed to store adjustment data for setting a resistance of said second resistor at a designed resistance, which is specified based on the state of the control signal actually obtained when the resistance of the second resistor is set to a certain designed value. The storage unit is referred to for stored data to switch the second resistor to control the state of the control signal. In addition, the first resistor is switched to a resistance corresponding to the resistance of the second resistor.

Abstract: According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).

Abstract: Provided is directed to a method of accessing a word line of a semiconductor memory device, including the steps of: generating a word line active signal and an address strobe signal according to an active condition; receiving and decoding an address according to the address strobe signal; performing an active operation by accessing a word line in response to the word line active signal and the decoded address; holding after performing to decode a new address by receiving it during the active operation and another active operation; generating a precharge signal when a precharging condition is satisfied during a read operation; and accessing a new word line after performing the precharging operation according to the precharge signal.

Abstract: A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions.

Abstract: In write/erase verity operations of a memory transistor in a semiconductor memory, control of the semiconductor memory follows the following process. One main bit line is applied to be operative on the select side and another main bit line is applied to be operative on the reference side. On the select side, a sub bit line select transistor is turned on to select a sub bit line having connection to the memory transistor as a target for write/erase verify operations. The target memory transistor is turned on while the other memory transistors connected to the same sub bit line are turned off. On the reference side, a sub bit line select transistor is turned off to bring a sub bit line to a non-selected state.

Abstract: MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. A first conductive line functioning as a read line and extending in the X direction is connected to pin layers of the MTJ elements. A second conductive line functioning as a write line and read line and extending in the X direction is connected to free layers of the MTJ elements. A write line extends in the Y direction and is shared with two MTJ elements present above and below the write line. The two MTJ elements present above and below the write line are arranged symmetric to the write line.

Abstract: A semiconductor device includes a first detection circuit, a second detection circuit, a determination circuit and a pulse generation circuit. The first detection circuit detects the leading edge of the pulse waveform of an input signal. The second detection circuit detects the trailing edge of the pulse waveform of the input signal. The determination circuit determines whether the pulse width of the pulse waveform is shorter than a given period, based on detection results of the first detection circuit and the second detection circuit. The pulse generation circuit generates a pulse signal when the determination circuit determines that the pulse width of the pulse waveform is shorter than the given period.

Abstract: Memory interface methods and apparatus for processing source synchronous data from a memory device (DRAM). The methods and apparatus synchronously transfer data from the memory device to a memory controller even though the time variability of read return strobe signals is greater than one clock cycle.

Abstract: An apparatus and method for pre-charging an intermediate node for high-speed wordlines for accessing memory cells in high-speed memory arrays. The apparatus pre-charges a local capacitance located between a wordline supply voltage and the wordline to a voltage level that is greater than the wordline supply voltage. Once the wordline is selected, the charge stored on the local capacitance may be quickly shared with the capacitance of the wordline. The wordline supply voltage may be applied to the local capacitance to provide small, incremental voltage to move the wordline to its final voltage thereby improving the response time of the system.

Abstract: A memory device includes a material layer associated with at least one memory cell. The material layer is alterable to change the electrical resistance of the memory cell.

Abstract: A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit for driving a memory cell array for accessing memory cells of the dynamic memory for a refresh process. Furthermore, a storage circuit is provided, which is assigned to at least one of the memory cells, for storing a time information item with regard to a last previous access to the assigned memory cell during the operation of the memory, a register bit being set in a manner dependent on the stored time information item and being able to be evaluated for controlling a refresh process. The refresh control circuit calls up the time information item stored in the storage circuit during operation of the memory and accesses the memory cell array in such a way that the memory cell assigned to the storage circuit is refreshed in a manner dependent on the time information item.

Abstract: There is disclosed a semiconductor memory device which comprises a plurality of bit line pairs each having first and second bit lines arranged in a first direction, a cell array having a plurality of SRAM cells each of which is connected between the first and second bit lines of a corresponding bit line pair via first and second storage nodes, respectively, a plurality of word lines arranged in a second direction crossing the first direction, and a data write circuit which, in the write mode, writes data into an SRAM cell selected by a word line via the first and second bit lines and, in the read mode, rewrites data read onto the first bit line from an SRAM cell selected by a word line onto the first bit line.

Abstract: A III-V nitride blue laser diode has an amplifier region and a modulator region. The amplifier region has a constant current to keep the region near the lasing threshold. The modulator region has a small varying forward current or reverse bias voltage which controls the light output of the laser. This two section blue laser diode requires much lower power consumption than directly modulated lasers which reduces transient heating and “drooping” of the light output.