Abstract: A sense amplifier of this invention has a main characteristic feature in that it has low power consumption in an input waiting state, and can perform a highspeed sensing operation. The sense amplifier includes an output transistor, a constant current source connected between the base of the transistor and a first power source, a MOS transistor, having a source-drain path connected between the base of the transistor and a second power source, for receiving most of a current from the constant current source, and a load resistor for the transistor. The base potential of the output transistor in the input waiting state is set to be a value corresponding to a state immediately before or after the transistor is turned on.

Abstract: A pulse detector keeps track of the peak value of an analog input signal and clocks output data pulses into a flipflop and shift register at peak values thereof while it monotonically increases in magnitude for each polarity. The data input to the flipflop becomes logic zero once the analog input signal changes direction toward the opposite polarity, whereby the last output data pulse in the shift register corresponds to the maximum peak of the analog input signal during the given polarity.

Abstract: Voltage sensing brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential.The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: A combined sense amplifier and latching circuit receives an input signal (VIN) at an input terminal (22). A sense amplifier includes a gated-loop type master latch (ML) having two cascaded inverters (I12, I13) with a common node (I) coupled therebetween and a control device (TG4) in the master latch loop controlled by a gating signal (55A). A reference voltage generator generates a reference voltage (VREF). The two inverters are biased between a first supply voltage (Vdd) having a magnitude greater than the reference voltage and either a second supply voltage (GND) or the reference voltage depending on the value of the gating signal. The input terminal is connected to the input of one of the inverters. A gated-loop slave latch (SL) is connected in series with the sense amplifier and includes two cascaded inverters (I14, I15) with a common node (M) coupled therebetween and a control device (P15) in the slave latch loop controlled by the gating signal.

Abstract: A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.

Abstract: A level changing semiconductor integrated circuit includes two current paths in which emitters of first and second bipolar transistors are each connected in series to one terminal of first and second MOSFETs, respectively. The current paths are disposed between a high-potential power source and a low-potential power source. Gates of the first and second MOSFETs are cross-connected to the emitters of the bipolar transistors of opposite current paths. The emitters of the first and second bipolar transistors provide output signals. At least two different types of input signals having different signal levels are simultaneously applied to respective input units of the current paths.

Abstract: A circuit for detecting a variation in power supply voltage includes first transistor (PM1) arranged as a current source and connected to the input (K1) of a current mirror (NM1, NM2), whose output (K2) is connected to a second transistor (PM2) arranged as a current source and to the output of the circuit. In the event of a temporary decrease in supply voltage this circuit will produce a pulse-shaped signal on its output, which signal can be employed as a trigger signal such as a reset signal in bistable circuits.

Abstract: A cascode logic circuit provides a pair of differential output nodes that are pulled up by a pair of cross-coupled P-channel output transistors. The output nodes are connected to outputs of an N-channel combinatorial network that receives a differential input and functions to connect one of the output nodes to a positive supply and the other to ground, depending upon the differential input, thus providing a push-pull effect. The output nodes may be connected to the differential output of the combinatorial network by source-drain paths of separate N-channel transistors, with the gates of these transistors connected to the positive supply to capacitively isolate the output nodes from the combinatorial network; alternatively, the gates of these transistors may be clocked. A fully static latch is provided by adding cross-coupled N-channel transistors connecting the output nodes to ground, so the low side of the output is held down instead of being allowed to float.

Abstract: An analog switch comprises first and second FET switches connected in series between input and output terminals through a first interconnection point, a third FET switch connected between the first interconnection point and one of power terminals, fourth and fifth FET switches connected in series between input and output terminals through a second interconnection point and a sixth FET switch connected between the second interconnection point and the other of the power terminals, whereby the first, second and sixth FET switches are simultaneously turns on or off in a manner that their operating conditions are kept in phase opposite to the third, fourth and fifth FET switches.

Abstract: A data output buffer being capable of precharging a data bus without increasing its current consumption and without having great dependency upon the process variation, whereby a READ access time of a semiconductor device is considerably reduced and the noise of source supplying voltages (Vcc, Vss) is also controlled to its least possible level in a semiconductor chip. The buffer includes means for minimizing the DC current consumption of a data bus precharge driver by feeding back an electric potential of an I/O port to an input of the precharging driver, and means for making the precharge driver operate during a specified period of time prior to providing the actual data by using an ATD pulse.

Abstract: A highly integrated Bi-CMOS logic circuit using MOS transistors and Bipolar transistors, the circuit including a number of input terminals for inputting signals, an equal number of MOS transistors having drain-source current paths connected in series and each having a gate controlled by a corresponding one of the input signals, and an equal number of MOS transistors having drain-source current paths connected in parallel and each having a gate controlled by a corresponding one of the input signals. Two bipolar transistors are base-controlled by the MOS transistors.

Abstract: An emitter follower current switch circuit is provided for emitter coupled logic or current mode logic (ECL/CML) circuits having output buffer emitter follower transistor elements which source true and complementary output signals of high and low potential to respective true and complementary outputs of the ECL/CML gate. The emitter follower current switch circuit effectively disconnects the output current sink from and ECL/CML gate output and corresponding output buffer emitter follower transistor element when the corresponding output is at high potential. At each output a current switch transistor element is coupled between the respective output buffer emitter follower transistor element and the output current sink. A control circuit controls the conducting state of the current switch transistor element so that it is on (conducting) or off (non-conducting) for corresponding output signals of low and high potential respectively.

Abstract: The logic has an extremely high speed, very low number of components and large common mode rejection, and is intended to eliminate the emitter-coupled logic (ECL). The supply voltage and power consumption are small. The logic is particularly for digital systems requiring extremely fast and complex digital processing, such as supercomputers. One basic gate is responsive to and providing differential binary signals, and comprises a pair of transistors of opposite conductivity types, each having a base, emitter and collector, wherein the bases are separately coupled to gate inputs, the emitters are coupled together, and the collectors are separately coupled to gate outputs and further to a power supply via biasing resistors. Based on the basic gate is a memory cell which includes a positive feedback resistor and can be read and written via a single terminal.

Abstract: A MOS high side driver circuit switching a supply voltage by means of a power switching transistor M1 driven by a driving circuit in function of a drive switching signal C, utilizes a flip-flop for driving the gate of the power switching transistor M1. The inputs SET and RESET of the flip-flop are respectively connected to the drain node of two, grounded source, input transistors supplied from a V.sub.GG rail maintained at a constant potential difference from the source (output) node of the power switching transistor M1. Two pulse signals C.sub.R, C.sub.S and corresponding to a rising and to a falling edge of the drive switching signal C from which they are derived by suitable circuit means, are respectively applied to the gates of the two input transistors. The driving circuit dissipates only during transitions in contrast to the driving circuits of the prior art.

Abstract: A detector circuit for detecting a state change of an unknown binary signal has a control circuit generating two pulse sequences which are shifted in time against each other and two flip-flops. The first pulse sequence activates the first flip-flop and clears the second one, whereas the second pulse sequence activates the second flip-flop and clear the first one. Therefore, the two flip-flops are prepared to trigger on transitions of the unknown binary signal to be tested alternatingly. Such a detector circuit can be used to avoid undue restrictions caused by the necessary recovery time of a single flip-flop.

Abstract: A TTL output driver gate configuration which has reduced voltage spikes on internal power supply potential and ground potential nodes includes a P-channel pull-up transistor (P1), an N-channel pull-down transistor (N1), a NAND logic gate (14), a NOR logic gate (16), a first positive feedback amplifier circuit (18), and a second positive feedback amplifier circuit (20). The pull-up transistor (P1) and the pull-down transistor (N1) have gates which are made serpentine. The reduction of voltage spikes is achieved by slowing down the turn-on times of the pull-up and pull-down transistors during transitions due to the distributed resistances and capacitances of the polysilicon material used to form the serpentine gates thereof. The first and second positive feedback amplifier circuits (18, 20) are used to pull the undriven gate ends of the respective transistors all the way to negative and positive supply potentials so as to facilitate transitions at an output node.

Abstract: A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage, clamping circuitry, an output stage and feedback circuitry. The clamping circuitry clamps the voltage level presented to the output stage at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the CPI circuitry rises, feedback circuitry feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the specified voltage level from 1.51 and 2.2 volts. The feedback circuitry contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry, and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage thereby reducing noise on the power supply and ground lines.

Abstract: A reset circuit for a logic circuit comprises a MOS transistor having a gate coupled to a power supply, a source receiving a reset input and a drain whose potential is high when the reset input is high and the power supply voltage drops below a predetermined threshold, a flip-flop connected to be set when the drain of the MOS transistor is high and reset when the reset input is low, and a circuit producing a reset output when the flip-flop is in the set state, the reset output being applied to the logic circuit.