Abstract: A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer starting at a data buffer start address until the address of said last item.

Abstract: A programmable visualization apparatus processes graphical data. The apparatus includes a central processing unit for executing a visualization application and a scheduler. A third level of memory is connected to the central processing unit. The third level of memory stores the graphical data. The graphical data is partitioned into a plurality of blocks. A second level of memory is connected to the central processing unit by a system bus. The second level of memory stores a sub-set of the plurality of blocks. A first level of memory is connected to the second level of memory by a memory bus. The scheduler stores an ordered list of blocks in the first level memory. A processor element is connected to the first level of memory by a processor bus. A dispatcher is connected to the first, the second, and the third memories and the processor element. The dispatcher transfers blocks from the third, to the second, and from the second to the third level memories according to the order of the list of blocks.

Abstract: A computer system splits a data space to partition data between processors or processes. The data space may be split into sub-regions which need not be orthogonal to the axes defined the data space's parameters, using a decision tree. The decision tree can have neural networks in each of its non-terminal nodes that are trained on, and are used to partition, training data. Each terminal, or leaf, node can have a hidden layer neural network trained on the training data that reaches the terminal node. The training of the non-terminal nodes' neural networks can be performed on one processor and the training of the leaf nodes' neural networks can be run on separate processors. Different target values can be used for the training of the networks of different non-terminal nodes. The non-terminal node networks may be hidden layer neural networks.

Abstract: A race standings display is disclosed having a base which supports a square, vertical tower. A series of two-digit LED number displays is arranged vertically along the tower, showing first elapsed time (four digits for this display), then a lap count, and then competitor numbers in order of their position in the race. Optionally, red, green and yellow LEDs may be provided to indicate the status of the race (e.g. yellow for racing under a caution flag). The back of the standings display pylon is provided with connectors for power and a phone line, and optionally, connectors for a 10 keyboard and monitor. A computer or microcontroller in the standings display is programmed to establish a phone connection to a real-time database (preferably via the internet), and is programmed to automatically update the standings display during the progress of the race. During times when a race is not in progress, the standings display may act as a regular clock and display car numbers in order of current point standings.

Abstract: A method of compressing programs, especially those used in embedded systems, is provided which allows greater program compression without significantly degrading system performance. The method provides: first, examining an entire program for sequences of lines of code, which may or may not constitute basic blocks; determining which sequences are identical or are identical except for a variation in a predetermined number of Elements within the sequence; designating and saving one uncompressed version of the identified sequences in memory as a specific microroutine, saving the Elements which differentiate the saved sequence from the various nearly identical sequences; and, assembling a version of the program consisting of original lines of code and microcalls. The microcall is a line of code which instructs a processor to implement a previously saved microroutine and provides an indication as to which Elements in the microroutine are to be replaced and where to find the substitute Elements.

Abstract: Disclosed is a host adapter having automatic termination, and a method for implementing the automatic termination. The host adapter includes a first connector for connecting to at least one external peripheral device and a second connector for connecting to at least one internal peripheral device. The host adapter further includes a termination system circuit that is coupled between the first connector and the second connector. The termination system circuit is configured to produce bit data that is indicative of whether a peripheral device is coupled to one or both of the first connector and the second connector. Preferably, the termination system circuit communicates the bit data to a software termination engine upon boot-up to enable or disable a termination of the host adapter. Furthermore, the termination system circuit includes a termination control decoder and a tri-state buffer.

Abstract: A redundancy circuit for a semiconductor integrated circuit is disclosed, which includes each cell of the column redundancy cell block corresponding to each cell of the cell sub-array is connected opposite to the connection of the cells of the cell sub-array, wherein a state that an electric charge corresponding to a data written into each cell of the cell sub-array and the column redundancy cell block is discharged, is measured for thus accurately checking the position of the repaired cell after the redundancy operation is performed.

Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e.