Patents Examined by Magid Y. Dimyan
  • Patent number: 8051397
    Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: November 1, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
  • Patent number: 8020133
    Abstract: A semiconductor integrated circuit according to an embodiment of the invention includes a single-cut via 60 and a multi-cut via 30 that includes a first via 30a and a second via 30b. An overhang (OHa or OHb) with respect to at least one of the first via 30a and the second via 30b is smaller than an overhang OH with respect to the single-cut via 60.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichi Nishimuda
  • Patent number: 8015538
    Abstract: The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas D Coolbaugh, Xuefeng Liu, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
  • Patent number: 8010925
    Abstract: The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement process which arranges the cells in the bins to obtain a legal arrangement while generating simply connected free space for routing channels.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Markus Buehler, Juergen Koehl
  • Patent number: 8001505
    Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: August 16, 2011
    Assignee: Synopsys, Inc.
    Inventors: Manoj Bist, Sandeep Mehrotra
  • Patent number: 7996797
    Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: August 9, 2011
    Assignee: Altera Corporation
    Inventors: Deshanand Singh, Valavan Manohararajah, Gordon Raymond Chiu, Ivan Blunno, Stephen D. Brown
  • Patent number: 7996802
    Abstract: A method of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit including a plurality of logic circuits and at least one connection line between the logic circuits, the method includes: obtaining information of a plurality of pieces of asynchronous circuits from the circuit information; determining information of asynchronous circuits of a first type and a second type stored in a library; extracting information of an asynchronous circuit of a third type including the asynchronous circuits of the first type and the second type; and extracting verification information associated with the information of the asynchronous circuit of the third type, for verifying the circuit.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 9, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Noriyuki Ikeda, Takashi Matsuura
  • Patent number: 7987437
    Abstract: A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Bernard C. Drerup, Richard Nicholas
  • Patent number: 7979837
    Abstract: Methods for analyzing circuit distortion based on contributions from separate circuit elements are presented. Local approximations that do not require high-order derivatives of device models are developed near an operating point for calculating distortion summaries including compression summaries and second-order intermodulation (IM2) distortion summaries.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: July 12, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Fangyi Rao, Dan Feng
  • Patent number: 7975250
    Abstract: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Hooman Honary, Inching Chen, Ernest T. Tsui
  • Patent number: 7975252
    Abstract: The present invention relates to a method for finding design weakness and potential field failure of a PCB assembly which includes components, comprising the steps of: (a) creating a model of the PCB assembly by which natural frequencies and mode shapes of the PCB assembly can be determined; (b) performing a natural frequencies simulation for determining natural frequencies and mode shapes of the PCB assembly; and (c) analyzing said determined natural frequencies and mode shapes and identifying local dominant oscillations of components, components identified as having a local dominant oscillation in at least one of said determined mode shapes are identified as components having a relatively high potential of field failure.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: July 5, 2011
    Inventor: Abraham Varon-Weinryb
  • Patent number: 7971161
    Abstract: A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Mary D. Brown, William E. Burky, Todd A. Venton
  • Patent number: 7971165
    Abstract: A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Noriko Yabumoto, Akiko Satoh, Zhengjun Zhang, Takashi Matsuura
  • Patent number: 7971160
    Abstract: A method for creating a pattern on a photomask includes steps of recognizing a space between main patterns by using pattern data which indicate the main patterns to be adjacently transferred onto a wafer, determining a 1st rule about arrangement of an assist pattern on the photomask, the assist pattern being adjacent to the main patterns and not being transferred onto the wafer, estimating a depth of focus in the presence of the assist pattern among the main patterns, determining a 2nd rule about arrangement of the assist pattern on the photomask to improve the depth of focus in the presence of the 1st assist pattern among the main patterns in a group having one or more number of appearance times of the space between main patterns, and correcting the assist pattern on the photomask using the assist pattern data on the basis of the 2nd rule.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Morimi Osawa, Takayoshi Minami, Satoru Asai
  • Patent number: 7971176
    Abstract: A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Rao H. Desineni, Maroun Kassab, Franco Motika, Leah Marie Pfeifer Pastel
  • Patent number: 7966596
    Abstract: This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: June 21, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lee-Chung Lu, Chung-Hsing Wang, Ping Chung Li, Chun-Hui Tai, Li-Chun Tien, Gwan Sin Chang
  • Patent number: 7962885
    Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: June 14, 2011
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
  • Patent number: 7962871
    Abstract: An apparatus, program product and method perform static timing analysis on an integrated circuit design by concurrently modeling a plurality of timing delays associated with a connection between points in the design. The delays are conveyed in multiple clock signals of a single timing run of a static timing analysis operation. Multiple paths comprising logical user defined delay segments are assigned different delays. Only one signal may be permitted to propagate along each path.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Craig M. Darsow, Timothy D. Helvey
  • Patent number: 7958469
    Abstract: A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Jieming Qi
  • Patent number: 7958466
    Abstract: A method for generating a scalar quality metric value for a design solution includes reflectings one or more qualities of the design solution with respect to two or more domains in the system. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 1, 2006
    Date of Patent: June 7, 2011
    Assignee: Altera Corporation
    Inventor: Ryan Fung