Abstract: There is disclosed a solid-state imager for preventing an unwanted potential barrier in the overflow control gate when ions are implanted into the sensor portion. The imager is capable of easily controlling the amount of overflow. The sensor portion takes the hole accumulation diode (HAD) sensor structure. A potential barrier is created in the overflow control gate by ion implantation. A potential difference created between the overflow control gate and the sensor portion is determined by the amount of ions implanted. A DC voltage V.sub.D applied to the overflow drain is variable. The potential difference is adjusted by varying the DC voltage V.sub.D. Thus, elements of the imager are uniform in potential barrier.

Abstract: Improved non-volatile memory cells capable of being written and erased electrically, suitable for high density low voltage applications are disclosed. Writing the cells is by using the Channel Accelerated Carrier Tunneling (CACT) method for programming memories, (patent application Ser. No. 08/209,787 filed on Mar. 11, 1994) and the erase is by tunneling through a thin oxide region. Two structural embodiments are disclosed. First embodiment, Trenched-Channel Accelerated Tunneling Electron cell (Tr.sub.-- CATE), and a second embodiment Trench Wall-Channel Accelerated Tunneling Electron cell (Tw-CATE), both make use of separate regions of the channel for write and erase and hence provide high reliability of operation. The cells disclosed use a vertical step etch to form part of the channel to accelerate the carriers and also to act as a select gate without increasing the cell area.