Patents Examined by Majid A. Banakhah
  • Patent number: 6684398
    Abstract: One embodiment of the present invention provides a system that facilitates entering and exiting a critical section of code for a speculative thread. The system supports a head thread that executes program instructions, and the speculative thread that speculatively executes program instructions in advance of the head thread. During an entry into the critical section by the speculative thread, the system increments a variable containing a number of virtual locks held by the speculative thread. Note that a virtual lock held by the speculative thread is associated with the critical section and is used to keep track of the fact that the speculative thread has entered the critical section. Also note that this virtual lock does not prevent the speculative thread or other threads from entering the critical section. During an exit from the critical section by the speculative thread, the system decrements the variable containing the number of virtual locks held by the speculative thread.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: January 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay
  • Patent number: 6263487
    Abstract: A programmable controller suitable for use in a globally distributed automation network. In addition, a universal management engineering and information system for such a globally distributed automation network is described. It is used in a globally distributed automation network.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: July 17, 2001
    Assignee: Siemens AG
    Inventors: Wolfgang Stripf, Volker Wendel
  • Patent number: 6260057
    Abstract: A method and apparatus for bypassing multiple pre-tests and post-tests during a system call when those tests are known to be inapplicable. One or more slow path flags are checked during a system call or TRAP. If the slow path flag is clear, execution follows a fast instruction path, resulting in faster execution for the system call or TRAP. Otherwise execution follows a slow instruction path. The slow path flags are set, cleared, and checked at appropriate times. The invention improves the execution time of a thread in a software process and may be used in a data processing system employing multiple threads. Each thread in the data processing system has its own set of slow path flags. The invention can set, clear and check the slow path flags of each thread independently, in subsets of threads, or in all threads.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: July 10, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Joseph R. Eykholt, Steven R. Kleiman
  • Patent number: 5630134
    Abstract: A multiprocessor system employs an inter-processor exclusive control apparatus. The inter-processor exclusive control apparatus has local areas formed in local memories, respectively, or in a shared memory, to store exclusive control data, as well as a shared area formed in the shared memory, to store exclusive control data. Executable unit processes manipulated by the multiprocessor system are optionally divided into groups that are associated with the local areas, respectively. The local memories are accessible only by the executable unit processes in the corresponding groups. The shared memory is shared by these groups. Each of the local areas manages exclusive requests from the corresponding executable unit processes. The shared area manages exclusive requests from the groups. Since the exclusive requests from the executable unit processes are managed by both the local areas and shared area, the number of accesses to the shared area is decreased because the shared area is accessible only by the groups.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: May 13, 1997
    Assignee: Fujitsu Limited
    Inventor: Yutaka Haga