Abstract: A data processing system includes a processor 46 operable to generate control signals to control one or more further circuits 4, 6 to adopt operational states to support different performance levels of the processor. The one or more further circuits generate current operation signals indicative of their current operation. Examples of further circuits are a clock generator 4 which generates a current operation signal indicative of a currently generated clock signal or possibly currently available clock signals. A voltage controller 6 may be a further circuit which serves to provide a power signal to the system and which generates a current operation signal indicative of the current maximum voltage level which the voltage controller is able to supply.

Abstract: A closed-loop based timing signal distribution architecture includes at least one signal source coupled to a signal path disposed in a closed loop arrangement to facilitate generation of a standing wave signal within the signal path. In one embodiment, at least one receiver is coupled to the signal path to generate at least one digital clock signal based upon the standing wave signal.

Abstract: An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.