Patents Examined by Mang-Ai T. An
  • Planar cache layout and instruction stream therefor
    Patent number: 6131152
    Abstract: Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met using a cache structure which includes a device for storing a shuffled instruction stream; and a device for multiplexing bits from the storage means onto the bus so that the bits are deshuffled. The multiplexing means includes a multiplicity of lines leading from the storage device to the bus. The read lines do not cross each other.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: October 10, 2000
    Assignee: Philips Electronics North America Corporation
    Inventors: Michael Ang, Eino Jacobs