Abstract: A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space.

Abstract: A method and apparatus used within memory and data processing that reduces the number of references allowed in processor cache by using active rows to reject references that are less frequently used from the cache. Comparators within a memory controller are used to generate a signal indicative of a row hit or miss, which signal is then applied to one or more demultiplexers to enable or disable transfer of a memory reference to processor cache locations. The cache may be level one (L1) or level two (L2) caches including data and or instructions or some combination of L1, L2, data, and instructions.

Abstract: A mechanism is provided within a 3D stacked memory organization to spread or stripe cache lines across multiple layers. In an example organization, a 128B cache line takes eight cycles on a 16B-wide bus. Each layer may provide 32B. The first layer uses the first two of the eight transfer cycles to send the first 32B. The next layer sends the next 32B using the next two cycles of the eight transfer cycles, and so forth. The mechanism provides a uniform memory access.

Abstract: A device is connected between an storage device controller and a storage device, providing data storage device protection in a manner transparent to the computing system and to the user of the computing system independent of operating system. The device protects the user from malicious code by preventing its execution and the unauthorized or unwanted user data modification by making the contents of one of the storage device read only. All the operations of the device are invisible to the computing system and to the user independent of installed operating system. The device can be disabled by a switch or by other means. When this happens the effect is the same as if the device were physically removed of the computing system.

Abstract: Each CM retains a function management table in which entry information indicating which function is operating in which CM for what period is registered. Every time a command is executed in a function processing unit on the basis of an instruction from a GUI, components of a CM perform control, communicating registered pieces of content in a function management table to corresponding components of another CM for synchronization among the CMs. Regardless of which of a plurality of CMs in a storage apparatus is a master, processing can be executed in any CM from any GUI without inconsistency in the processing between the CMs.

Abstract: A control apparatus connectable to a memory unit for storing data, for controlling a first tape writing unit including a plurality of first tapes and a second tape writing unit including a plurality of second tapes so that the first and second writing units write same data stored in the memory unit to one of the first tapes and one of the second tapes, respectively, has an obtaining unit for obtaining a progress value indicating a progress of writing data into the one of the second tapes upon completely writing the data into one of the first tapes and a controller for controlling the first and the second tape writing units so that the first and the second writing unit change the writing tapes to another of the first tapes and another of second tapes when the progress value being not more than a predetermined value.

Abstract: A computer includes an enclosure, an internal mass storage device within the enclosure, and a redundancy controller within the enclosure. At least one port enables direct connection of the computer to at least one external mass storage device. The redundancy controller is configured to provide data redundancy using the internal mass storage device and the at least one external storage device if the at least one external mass storage device is connected to the at least one port.

Abstract: A data management system and data management method capable of inhibiting an increase of I/Os caused by deduplication are provided. Data blocks are managed by grouping them; a plurality of chunks belonging to the same group after deduplication are collectively managed as a chunk data set; and if a host system issues a data block deletion request, garbage collection of the relevant chunk data set is performed based on the number of times of references of the chunk data set and the chunk data set after the garbage collection is managed by overwriting the existing chunk data set with a new chunk data set composed of only chunks of data blocks which are not deleted.

Abstract: A method includes receiving a message to be logged. In response to receiving the message, the message is written to a stream corresponding to an active archive. The active archive includes compressed messages. Also in response to receiving the message, the message is written to an active log without compression.

Abstract: A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.

Abstract: A graphics system is provided that utilizes a tree-structured organization of graphic segments (a-m) which potentially overlap when presented as a two-dimensional image. Each child segment in said organization inherits image-related spatial transformations to which its parent is subject. To increase flexibility of representation using such a tree organization, provision is made for associating parent and child segments (c;b,d) by an attachment relationship that determines that outside of the boundary of the parent (c) in said image, the child (b,d) is unrestricted by its parent. This relationship may either be an "above" or "below" attachment relationship (40,42) depending on whether the child or parent has a higher depth priority where the segments overlap.