Abstract: The method and apparatus disclosed herein relates to parallel implementation of a combinatorial optimization in a multiprocessor network. The system operates as an intermediary between a root processor and a multiprocessor network. The system generates shadow nodes which are used to occupy idle capacity available within the multiprocessor network. Particularly, the shadow nodes are used to refine solutions for enumerative problems, search graph and the like while providing a near 100% utilization of a processor time in a multiprocessor network. The system provides a fully asynchronous and homogenous system design to enable the creation of locally ordered expansion queues.

Abstract: A device interface module provides multiple concurrently operating data transfer channels between multiple groups of peripheral devices and ad multiported buffer memory which communicates via an interface bus to other external modules of a computer system.

Abstract: An apparatus for conditioning signals output from a computer system expansion card to a computer system board to test system board bus specifications and timing limits. The apparatus comprises two signal conditioning extension cards which are used to condition signals from a slave card and a bus master card. The signal conditioning extension cards according to the present invention are interposed between the bus master or slave expansion card and the system board and selectively advance or delay the signals output from the expansion card to the system board. The slave signal conditioning card also selectively delays the read data valid window of the slave card to test the limits of the system board. The bus master signal conditioning card selectively delays the write data valid window of the bus master card to test the limits of the system board.