Patents Examined by Marcel Pruessner
  • Patent number: 6038382
    Abstract: When deciding on cell allocation, the existing cut position is searched for using an existing cut position deciding module. The balance of the existing cuts is incorporated into its restriction requirements using a restriction requirements judging module and the Min-cut method. When deciding on the cell allocation, a cost function calculating module uses such a cost function as to reduce the resulting cost when the existing cuts are balanced using the existing cut position, which has been obtained using the existing cut position deciding module. Then the Min-cut method based on this cost function is executed.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: March 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Yuzi Kanazawa
  • Patent number: 6011912
    Abstract: In an automatic routing method for layout design, the present invention reduces wastful detours or bends of the routing paths, so that it also reduces non-completed paths, that cannot be completed without rip-up and rerouting. All nets are provisionally routed in such a manner as to allow more facilitated evasion of collision such as shorting between nets (step 15). The net order is then set (step 16). If collision between nets is found, the processing order is changed so that a net which is judged to allow for more facilitated evasion of collision will be finalized later. The routing paths are then finalized net by net (steps 17 to 20). The shape of the colliding path, for example, is used as a criterion for judging ease in evasion.
    Type: Grant
    Filed: August 12, 1997
    Date of Patent: January 4, 2000
    Assignee: NEC Corporation
    Inventors: Nobuyasu Yui, Hiroyoshi Yamazaki
  • Patent number: 6009252
    Abstract: A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to generate color symmetrizing matrices corresponding to respective child cells in the integrated circuit schematic. Here, the child cells are characterized as having a number of symmetrical configurations which at a port level are electrically equivalent. Operations are also performed to generate a first color symmetry vector for a child cell in the integrated circuit schematic and a second color symmetry vector for the corresponding child cell in the integrated circuit layout. A vector equivalency is also preferably determined by comparing a product of the color symmetrizing matrix and the first color symmetry vector against a product of the color symmetrizing matrix and the second color symmetry vector.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: December 28, 1999
    Assignee: Avant! Corporation
    Inventor: Gary Bruce Lipton