Abstract: The novel credit-based adaptive flow control method and system for multi-stage, multi-dimensional, data switching architecture. The method and system of the present invention estimates and balances data flow in the switch architecture by using statistical information derived from the normal switching operation without requiring specific information from the previous stage. The multi-stage multi-dimensional switching architecture of the present invention includes three stages. The first and third stages are the buffering stages, and the second stage acts as a buffer-less crossbar switch node. Each stage includes an array of switching elements, and each element includes either a queuing processor or an arbitration processor arranged to progressively refine estimates of the data traffic from switch elements in the first stage by the second stage. The second stage maintains the statistic of valid traffic arrival and departure, and feedback grant information bit to the first stage.

Abstract: The present invention relates to methods for changing the bandwidth of a circuit switched channel in a time division multiplexed network, wherein said channel comprises a set of time slots within each recurring frame of a bitstream between a first node and a second node. According to the invention one or more additional time slots within each recurring frame of said bitstream are reserved, including using, during a period of time, only said set of time slots for transmitting payload data pertaining to said channel while providing, during said period of time, information indicating that said one or more additional time slots are currently not used for transferring payload data. After said period of time, said set of time slots is used as well as said one or more additional time slots on said bitstream for transmitting payload data pertaining to said channel.

Abstract: Methods and apparatus for interleaved weighted fair data packet queue sequencing are disclosed. An interleaving table specifies a queue sequence. A queue sequencer follows the table order on an epoch-by-epoch basis, selecting a queue for each epoch based on the table order. If the selected queue does not have enough data to fill its epoch, the sequencer can step to the next queue in the table order. Because the table is interleaved, higher-priority queues can be visited frequently, improving jitter and latency for packets associated with these queues. The table structure allows all queues at least some portion of the available output bandwidth, and can be organized to afford some queues a much larger portion without having those queues monopolize the output stream for inordinate amounts of time. In some embodiments, each table entry has a programmable epoch value associated with it. The epoch value can be used to weight each table entry respective to the other entries.