Abstract: A microphone array is described for use in ultra-high acoustical noise environments. The microphone array includes two directional close-talk microphones. The two microphones are separated by a short distance so that one microphone picks up more speech than the other. The microphone array can be used along with an adaptive noise removal program to remove a significant portion of noise from a speech signal of interest.

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.

Abstract: A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.

Abstract: A semiconductor device includes a substrate including a first active area extending in a first direction and a second active area extending in a second direction and connected to the first active area; first and second gate structures respectively crossing the first and second active areas; a first region in an area where the first and second active areas are connected to each other, the first region being on a first side of each of the first and second gate structures; a second region in the first active area on the other side of the first gate structure; and a third region formed in the second active area on the other side of the second gate structure.

Abstract: A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.

Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.

Abstract: A method for manufacturing a semiconductor device includes: forming a first patterned target layer on a substrate having a first region and a second region, the first patterned target layer having first openings along a first direction in the first region; forming a patterned hard mask layer over the first patterned target layer and having first recesses along a second direction in the first region and second recesses along the first direction in the second region; forming a patterned photoresist layer over the patterned hard mask layer and having stripe structures along the second direction in the first region and block structures along the first direction in the second region; and etching the patterned photoresist layer, patterned hard mask layer, and first patterned target layer to form a second patterned target layer.

Abstract: A FinFET device includes a strain relaxation buffer (SRB) substrate. A set of cut silicon fins is on the SRB substrate. Each fin in the set of cut silicon fins has a pair of long vertical faces and a pair of short vertical faces. Pairs of the cut silicon fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other. A set of cut silicon germanium fins is on the SRB substrate. Each fin in the set of silicon germanium fins has a pair of long vertical faces and a pair of short vertical faces. Pairs of the cut silicon germanium fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other. A set of tensile dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon fins to maintain tensile strain at the fin ends of the pair of cut silicon fins.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

Abstract: One aspect of the invention relates to a chip assemblage. The latter comprises a number of semiconductor chips, each of which has a semiconductor body having an underside, and also a top side, which is spaced apart from the underside in a vertical direction. A top main electrode is arranged on the top side and a bottom main electrode is arranged on the underside. Moreover, each of the semiconductor chips has a control electrode, by means of which an electric current between the top main electrode and the bottom main electrode can be controlled. The semiconductor chips are connected to one another by a dielectric embedding compound to form a solid assemblage. The chip assemblage additionally comprises a common control terminal, and a common reference potential terminal.

Abstract: An organic light emitting diode display includes: a substrate; a scan line formed over the substrate and transmitting a scan signal; a data line crossing the scan line and transmitting a data voltage; a driving voltage line crossing the scan line and transmitting a driving voltage; a switching transistor connected to the scan line and the data line; a driving transistor connected to the switching transistor; a driving connection member connected to a driving gate electrode of the driving transistor; a storage capacitor including a first storage electrode and a second storage electrode; a pixel electrode electrically connected to the driving transistor; and a contact hole connecting the first storage electrode and the driving connection member. the second storage electrode may include a cut-out by a curved edge at least partially surrounding the contact hole, and the pixel electrode may be formed not to overlap the cut-out.

Abstract: A method for fabricating a semiconductor device including: forming a block layer above a well region of a first doping type in a semiconductor substrate, wherein the block layer has an opening for defining a first region in an upper part of the well region and has sidewalls at sides of the opening; implanting dopants of a second doping type into the well region through the opening of the block layer to form the first region; implanting dopants of the first doping type into the first region in the manner of large-angle-tilt dopants implantation to form a second region for a first transistor, and to form a third region for a second transistor; and forming, for both of the first transistor and the second transistor, a fourth region between the second region and the third region.

Abstract: Provided is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked.

Abstract: A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a semiconductor package and a display apparatus which include the semiconductor chip are described. The semiconductor chip includes a circuit region disposed in a central part of a rectangle that is elongated in a first direction. The circuit region includes a plurality of driving circuit cells disposed at predetermined intervals in the first direction. A plurality of electrode pads is disposed around the circuit region, and a process pattern is disposed at at least one of the four sides of the rectangle.

Abstract: A method of processing a semiconductor substrate includes: immersing a substrate in a first bath, wherein the substrate comprises a barrier layer, a conductive seed layer, and a patterned photoresist layer defining an opening; providing a first electric current between the conductive seed layer and a first anode disposed in electrical contact with the first bath to deposit a conductive material within the opening; stripping the patterned photoresist layer; immersing the substrate in a second bath; providing a second electric current that is a reverse of the first electric current between the conductive seed layer plus the conductive material and a second anode disposed in electrical contact with the second bath; etching the conductive seed layer from atop a field region of the barrier layer; and etching the barrier layer from atop a field region of the substrate.

Abstract: A method for manufacturing a semiconductor device includes providing a wafer having a first semiconductor layer, forming at the first semiconductor layer a contact layer which includes a metallic chemical element, and implanting ions of a first chemical element different to the metallic chemical element into the contact layer.

Abstract: Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.

Abstract: A method for fabricating an LED light bar and an LED light bar are provided. The method includes: providing a transparent base, wherein at least one framework region for fixing LED chips is arranged on the transparent base, at least one milling groove parallel to the framework region is arranged at each of two sides of each framework region; arranging one or more LED chips on the at least one framework region; covering an upper surface and a lower surface of the transparent base where the LED chips are arranged with a packaging adhesive mixed with fluorescent powder, and filling up the milling groove with the packaging adhesive; and cutting the transparent base along the milling groove, to obtain an LED light bar surrounded by the adhesive.

Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.