Abstract: A light-emitting component is provided which comprises a carrier, a reflective layer and a light source, wherein the light source is mechanically fixed on a mounting surface of the carrier. The carrier has an electrically isolating basic body comprising an edge region, said edge region bounding the mounting surface. The edge region comprises a recess, wherein the reflective layer covers a base surface of the recess. Moreover, the mounting surface is vertically elevated with respect to the base surface of the recess at least in places, such that the reflective layer is kept away from the mounting surface. Furthermore, a method for producing such a light-emitting component is provided.

Abstract: A manufacturing method of a vertical GaN-based semiconductor device having: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity, which is lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant.

Abstract: A pattern is defined in a dielectric layer. The dielectric layer includes a low-k dielectric region and a high-k dielectric region. The high-k dielectric region includes a phase change material which is an alloy of tantalum and nitrogen and is a high-k insulator in a deposited state. The pattern includes a first set of features in the low-k dielectric region and a second set of features in the high-k dielectric region. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A metal layer is deposited in the first and second set of features. Thus, a set of conductive lines is formed in the low-k dielectric region and a metal insulator metal capacitor in the high-k dielectric region.

Abstract: An integrated micro-electromechanical device includes a first body of semiconductor material having a first face and a second face opposite the first surface, with the first body including a buried cavity forming a diaphragm delimited between the buried cavity and the first face. The diaphragm is monolithic with the first body. At least one first magnetic via extends between the second face and the buried cavity of the first body. A first magnetic region extends over the first face of the first body. A first coil extends over the second face of the first body and is magnetically coupled to the first magnetic via.

Abstract: Schottky structure fabrication includes forming two trenches in a semiconductor material. The trenches are separated from each other by a mesa. Sidewalls and a bottom surface of the trenches are lined with a dielectric material. A conductive material is disposed in the trenches lining the dielectric material on the sidewalls and the bottom surface. The conductive material on the bottom surface of the trenches is removed so that a first portion of conductive material remains on a first sidewall of each trench, and a second portion of conductive material remains on a second sidewall of each trench. The first and second portions of conductive material are electrically isolated from each other. The space between the first and second portions of the conductive material is filled with a trench filling insulator material and a Schottky contact is formed between the outermost sidewalls of the two trenches.

Abstract: The present invention provides a manufacturing method and a structure of an oxide semiconductor TFT substrate, in which an oxide conductor layer is used to define a channel and a source terminal of an oxide semiconductor TFT substrate. Since the oxide conductor layer is relatively thin and compared to the known techniques, the width of the channel can be made smaller and the width of the channel can be controlled precisely, the difficult of the manufacturing process of the oxide semiconductor TFT substrate can be reduced and the performance of the oxide semiconductor TFT substrate can be enhanced and the yield rate of manufacture can be increased.

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.

Abstract: An image sensor and a method of fabricating the image sensor are provided. The image sensor includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type. The deep well is formed at a predetermined depth in the semiconductor substrate to divide the semiconductor substrate into a first conductivity type upper substrate area and a lower substrate area. The image sensor further includes a plurality of unit pixels integrating charges corresponding to incident light and comprising first conductivity type ion-implantation areas. The first conductivity type ion-implantation areas are separated from one another. Moreover, at least one unit pixel among the plurality of unit pixels further comprises the first conductivity type upper substrate area that is positioned under a first conductivity type ion-implantation area included in the unit pixel.

Abstract: A semiconductor device capable of inhibiting a conductive plug from increase of resistance or disconnection resulting from moisture discharged from a first insulator film while reducing the capacitance between adjacent first interconnection layers is obtained. This semiconductor device comprises a plurality of first interconnection layers formed on a semiconductor substrate at a prescribed interval, a first insulator film, formed to fill up the clearance between the plurality of first interconnection layers, having an opening reaching the first interconnection layers and a conductive plug charged in the opening of the first insulator film and formed to be in contact with the first interconnection layers. An impurity is selectively introduced into a first region of the first insulator film in the vicinity of contact surfaces between the first interconnection layers and the conductive plug, thereby selectively modifying the first region of the first insulator film.

Abstract: This invention pertains to a method for removing heat from a heat source device and to a heat sink system characterized by a pressure bond having thermal resistance of less than about 5 K/kW-cm2. The method is characterized by the steps of removing heat from a heat source device comprising the steps of placing a heat source device in contact with a heat source and applying a sufficient force to form a pressure bond between the heat source device and the heat sink wherein thermal resistance at the interface between the heat source device and the heat sink after the thermal bond is established is less than about 5 K/kW-cm2. The heat sink system includes a heat source device and a heat sink in contact with the heat source device with thermal resistance at the interface of the heat source device and said heat sink is less than about 5 K/kW-cm2.

Abstract: Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.