Patents Examined by Marcos Pizarro
  • Patent number: 7405562
    Abstract: A detection apparatus for detecting the presence of a sample, the detection apparatus comprising a chamber, ports for introducing a sample within the chamber, an actuation unit for establishing a controllable electromagnetic field in the chamber; and a sensing unit for sensing changes in the electromagnetic field due to the presence of the sample within the chamber. The sensing unit comprises a sensor device comprising a source and a drain embedded in a FET a gate for the FET, in which the gate is formed of a material whose conductivity is related to the electromagnetic field established in a nonconductive medium in contact with the gate.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: July 29, 2008
    Inventors: Yehya Ghallab, Wael Badawy
  • Patent number: 7358139
    Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: April 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Andrew R. Bicksler, Sukesh Sandhu
  • Patent number: 7122869
    Abstract: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetical to the shape of the drain diffusion layer region thereof below the selection gate transistor.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: October 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshitake Yaegashi