Abstract: Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal.

Abstract: An input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external supply voltage, which includes an external supply voltage detecting unit for dividing the external supply voltage into a plurality of regions by comparing a plurality of voltages, which have been divided by different ratios of the entire external supply voltage, with a standard voltage; and a converting unit including a pull-up circuit and a pull-down circuit, for converting input signals of TTL level into signals of CMOS level, according to the regions of the external supply voltage obtained by the external supply voltage detecting unit.

Abstract: A power regulator for providing a fixed output voltage that is consistent with a reference voltage and independent of a varying power supply, includes a first input connected to a reference voltage generator; a second input adapted to be connected to a varying power supply; two outputs for connection to circuitry such as oscillators; a charge pump; and three transistors. The drain and gate of the first transistor are connected to the charge pump and the source is connected to the reference voltage generator; the gate of the first transistor is coupled to the gates of the second and third transistors; and the sources of the second and third transistors are coupled one of the two outputs.

Abstract: A technique for high speed transmission of digital signals on a bus line with reduced signal ringing, bounce and bus contention current. The approach uses a multi-partitioned driver design with temporary and steady state parts incorporating internal feedback and delay techniques to control the output slew rate. A built-in function outputs the driving status of the transceiver and allows the output to enter the high impedance status asynchronously.

Abstract: For determining a displacement of an object (41) from sheetlike material along an observing position (11, 12), each time the object (41) has been displaced over a particular distance, a pulse is generated. The passing object (41) is scanned, whereby a plurality of samples are generated between two pulses, independently of the displacement of the object (41), and to these samples moreover sequence information (37) is coupled. The number of samples between two pulses (39) and the number of generated pulses (38) are counted. The sequence information (37, 38) coupled to identified samples and the counted number of samples between two pulses (39) are used to determine the displacement of the object with greater accuracy than would be possible with the displacement-dependent pulses alone, without requiring that to this end interpolation pulses be generated and processed which are to be processed separately.

Abstract: A method and system for testing a digital counter of mn bits comprises dividing the counter into m segments, each of n bits. For test purposes, the counter then is further divided into first and second m segment groups. Multiplex gates are used between the segments and are controlled by sensing the condition of the most significant bits of the most significant one of the m segments for applying clock pulses to verify specific connections between various bits of the counter for the first four cycles of clock pulses applied during the test mode. After these four cycles, gating circuits coupled with the most significant bits of the most significant one of the m segments are used to automatically switch the remainder of the test connections to the second group to verify all of the remaining connections in the counter, with full testing of the counter being accomplished in 2.sup.n +2 cycles of clock pulses.

Abstract: A device for reliably counting and simultaneously marking objects includes an elongated housing, a container of marking fluid disposed within the housing, a fluid release mechanism associated with the container, and an axially moveable hollow spacer adapted to contact an object to be counted and marked and through which marking fluid is accurately directed onto the object. The spacer is rearwardly displaced by contact with the object, such displacement being detected by an electrical switch. An electronic controller, when activated by the switch, causes the release mechanism to emit a pulse of marking fluid, and at the same time registers an accumulating count.

Abstract: An output buffer circuit comprises a pair of first and second output MOS transistors coupled between a power supply line and a ground line; a booster circuit for boosting the power supply voltage up to a predetermined high voltage higher than a power supply voltage; a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors connected in series between an output side of the booster circuit and the ground line; and a level shifter circuit having a first terminal coupled to an output side of a first logic gate for receiving logic signals from the first logic gate, a second terminal coupled to the gates of the n-channel and p-channel MOS transistors of the complementary MOS circuit and a third terminal coupled to the output side of the booster circuit for receiving the predetermined high voltage from the booster circuit, the level shifter circuit performing to shift the logic signal of the logic gate up to at least almost the same level as the predetermined high voltage to supply a s

Abstract: An apparatus for branch detecting a loop operation in a microprocessor. The apparatus includes a register, an ALU port, a predetector, an ALU, a flag generator and a branch detector. The register is provided for storing a loop information. Through the ALU port, the loop information is sent to the predetector and is predetected therein whenever the loop operation is about to proceed. A predetected result is then generated by the predetected and is sent to the branch detector to determine whether the loop operation has to be terminated. The ALU processes the loop information and updates new loop the register at the same time the predetection and detection tasks are performed by the predetector and the branch detector, respectively. The flag generator generates a flag which is independent of the detection and termination of the loop operation.

Abstract: A method and apparatus is disclosed for reading data from and writing data to remote registers that are dispersed throughout an integrated circuit chip. Regardless of the size or number of remote registers involved, the operation is accomplished using only two interconnect lines, plus a clock. Each remote register is associated with a unique address. During a write operation, a microprocessor loads the write data into a staging register, loads the destination address into a header generation register along with a read/write control bit, and loads a count value into a clock. Thereafter, the apparatus of the invention proceeds automatically, as the clock counts down, to shift the data onto a serial data line following a header. Each of the remote registers in the system are arranged serially, and each monitors the header information, comparing the address contained in the header with its own address.

Abstract: A method and apparatus monitor the performance of a DDS loop connecting an information transmitter to an information receiver. The information transmitter is typically at a customer premises while the receiver is typically an OCU at the receiving local office. The DDS loop uses an alternate mark inversion communications protocol and the monitoring method and apparatus feature circuitry for determining a current imbalance on the DDS loop. The numbers of positive and negative pulses on the line are individually counted and if the count of the two counters used deviates either positively or negatively from each other by specified amounts, an error event is declared. If the error events meet a statistical timing criterion, a channel error is declared and appropriate steps are undertaken to prevent signals coming from the channel from interfering with other signals available at the local office.

Abstract: An integrated circuit pulse generator for per pin testing of electronic circuits. The pulse generator allows for independent adjustment of the slew rates of the rising and falling edges of the pulses. The pulse edges are generated by summing two separately controlled falling edge ramp generators. The circuit design of the pulse generator is structured to allow implementation with NPN transistors. The falling edge ramp generators operate by discharging a capacitor with a current source. The slew rates are varied by incrementally adding capacitance to the capacitor being discharged.

Abstract: A digital signal transmission circuit for transmitting an input pulse signal to receiving circuits through transmission lines. The digital signal transmission circuit is provided with a phase converting circuit for outputting a first output signal and a second output signal delayed in phase with respect to the first output signal according to the input of the pulse signal, a first transmission line included in the transmission lines, for transmitting the first output signal, a second transmission line included in the transmission lines, for transmitting the second output signal, and a pair of phase decoding circuits for receiving the first and second output signals from the first and second transmission lines and outputting pulse signals according to the state of reception of the first and second output signals.

Abstract: A pulse detection system for detecting pulses of sufficient magnitudes using a control detector providing crossing indications of pulses going beyond a threshold value, a stored threshold crossing adjustable actuator representing at least portions of selected crossing indications previously stored therein but reduced in magnitude as controlled by a magnitude reduction controller acting over time. An output detector may be used to detect signals going beyond another threshold.

Abstract: There is provided a method for counting and dispensing pills, tablets, and capsules which depends on a simple vibrating, sloped, concave-shaped (e.g., V-shaped) trough, having a number of descending steps. The vibration of the trough is controlled and adjusted by a microprocessor. The vibration of the trough is patterned to provide a greater vibratory amplitude at its dispensing end than at its intake end. The difference at each end of the trough in vibratory amplitude is achieved by elastomeric supports that are differently spring dampened. The microprocessor electronically adjusts the input vibration to the trough, such that the flow of materials is adjusted for different types of materials (i.e., tablets of different shapes and/or sizes). This causes the tablets to align accurately within the trough, and sequentially pass a pill detector mechanism in single file. This ensures that the device can handle an extremely varied range of tablet or capsule sizes and shapes.

Abstract: A clock system includes internal monitor circuitry such that the clock system is testable in a secure environment. In particular, the clock system includes a plurality of separately enableable clock generator circuit modules. Each of the clock generator circuit modules generates a separate clock signal when enabled. Combining circuitry receives the separate clock signals from those clock generator circuit modules which are enabled and derives a derived clock signal therefrom. Monitor circuitry receives the derived clock signal, detects whether there are transitions in the derived clock signal, and provides a monitor indication of a result of the detection. Thus, the clock system can be tested without providing the separate clock signals outside the clock system. Preferably, the clock system also includes a programmable clock control register that holds clock control data, the clock control data determining which of the clock generator circuit modules are enabled.

Abstract: Within an integrated circuit a source of digital data is coupled to a distant destination by a serial data path that is characterized by being either an imperfect and lossy transmission line or as possessing significant high frequency attenuation. A single phase clock accompanies the data over the serial data path. A single phase to three phase clock generator at the destination creates the three phase clock. If the destination is a shift register, then the three phase clock can be used for stage-to-stage clocking within the shift register, as well as for getting data into the input bit of the shift register.

Abstract: A signal transfer circuit for dynamic action with boot strap effect is formed with an inputting transistor Tr.sub.11 and a driving transistor Tr.sub.12 for driving a load Z.sub.1. To a gate electrode of a resetting transistor Tr.sub.13, a positive voltage V.sub.1 and a negative voltage V.sub.2 are alternately applied at 50% of duty ratio in synchronism with a shift pulse by transistors Tr.sub.15 and Tr.sub.16 connected in series between the positive voltage V.sub.1 and the negative voltage V.sub.2 and pulses .PHI..sub.1R and .PHI..sub.2R which are synchronous with shift pulses .PHI..sub.1 and .PHI..sub.2. When an output Q.sub.1 is HIGH level, a transistor Tr.sub.14 becomes conductive to force a gate voltage of the transistor Tr.sub.13 to 0 to release resetting.

Abstract: A process for evaluating acceptability of a digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the process comprising: generating a leading edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating a trailing edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating an accepted-rejected signal, functionally related to the width of the pulse.

Abstract: A quantized voltage is held by a holding circuit or a feedback circuit connected to a quantizing circuit so that a multi-valued voltage is registered. In another embodiment, outputs of bi-stable circuits with stopwise thresholds are added with weights introduced by a capacitive coupling.