Abstract: An output stage for a digital circuit for emitting a signal with the one or the other binary value in dependence upon an input signal includes an output transistor at the collector of which the signal to be emitted can be tapped off and to the base of which a current dependent on the input signal is supplied. In the line leading to the base of the output transistor, a device is disposed for setting the base current in dependence upon the current flowing through the collector-emitter path of the output transistor.

Abstract: An single power supply ECL to TTL/CMOS translator is provided for converting a signal from differential ECL logic levels to TTL or CMOS compatible logic levels without introducing current spikes in the output signal during logic transitions. The differential ECL input signal is transformed into first and second differentially related signals having predetermined differential and single ended magnitudes. The first and second differentially related signals are then buffered and applied, as independent single ended signals, to first and second conduction paths controlling the first and second switching circuits in an output stage, respectively.

Abstract: A high speed static single ended sense amplifier is disclosed, including, an input node, an output node, a first P-channel input transistor having its source connected to a source of positive voltage, its drain connected to the input node and its gate connected to a feedback node, a first N-channel input transistor having its drain connected to the input node, its source connected to a source of negative voltage and its gate connected to the feedback node, a first output P-channel transistor having its source connected to a source of positive voltage, its drain connected to the output node, and its gate connected to the feedback node, a first N-channel output transistor having its drain connected to the output node, its source connected to a source of positive voltage and its gate connected to the feedback node, an N-channel feedback transistor having its gate connected to the output node, its drain connected to a source of positive voltage and its source connected to the feedback node, a capacitive voltage d

Abstract: A substrate voltage bias generator is disclosed including a charge pump whose output is clamped during charge pump capacitor charging cycles to zero volts thereby eliminating a voltage drop associated with prior art clamping diodes. The charge pump further includes a stand-by and booted mode, the stand-by mode providing a first level of output current at a specified generated substrate bias voltage and in the booted mode generating increased output current and voltage. The increased voltage is generated across the charge pump capacitor by a second capacitor that is only operative in the booted mode and whose charge is shared with the charge pump capacitor thereby developing a higher voltage across the charge pump capacitor. The output voltage generated by the substrate bias generator is detected and if it is too low a voltage, the booted mode is turned off. An external signal determines whether the stand-by mode or booted mode are selected.

Abstract: An output buffer arrangement includes a first stable, controlled current source (MO1), a first bidirectional-switching device (24) including a CMOS transmission gate and being responsive to the first current source (MO1) for charging the gate of a pull-up transistor (MO5), a second stable, controlled current source (MO6), and a second bidirectional-switching device (27) including a second CMOS transmission gate and being responsive to the second current source (MO6) for charging the gate of a pull-down transistor (MO10). The output buffer arrangement reduces induced chip noise at low temperature, high power supply voltage without degrading substantially its high operational speed.

Abstract: A new family of memory cells and digital-logic gates use an enhancement-mode driver, a voltage-level shifter, and a current regulator to provide improved noise margins and large logic swings. The voltage-level shifter and the current regulator are connected in series between an input and the control electrode of the driver. The voltage-level shifter establishes a voltage drop which is independent of current, while the current regulator establishes a constant current in the series path to the control electrode which is independent of voltage. The driver is an enhancement-mode device, such as a JFET, MESFET, or BJT.