Abstract: An integrable evaluating circuit includes a trigger circuit, a first and a second circuit node, both of which serve both as inputs and as mutually-complementary outputs for the trigger circuit, a pair of signal lines exhibiting the same potential in a rest state, switching transistors each being connected between a respective one of the two circuit nodes and a respective signal line of the pair of signal lines, and a signal-enhancement circuit connected between the trigger circuit and the pair of signal lines. A signal occurring on a given one of the two signal lines is initially connected with its signal deviation to the circuit node connected to the given signal line. The switching transistor connected to the given one of the two signal lines is then blocked and cuts off the signal from the circuit node connected to the given signal line.