Abstract: There is provided a process for producing an integrated circuit, wherein not only can conductive fine particles be deposited efficiently and densely in minute wiring channels and connecting holes but also a circuit of low wiring resistance and high density can be formed and wherein a high-degree integration can be achieved to thereby bring about an economic advantage. In particular, there is provided a process for producing an integrated circuit, comprising coating a substrate provided with wiring channels with a coating liquid for integrated circuit formation containing conductive fine particles to thereby form an integrated circuit on the substrate, wherein the coating liquid for integrated circuit formation while being exposed to ultrasonic waves is applied to the wiring channels.

Abstract: A method for plasma processing of semiconductor wafers is provided that reduces plasma-induced damage to the gate dielectric while limiting damage to the wafer from particulates that flake off of the interior surfaces of the reaction chamber. Plasma conditions are maintained in the reaction chamber while the wafer is transferred into the chamber and the plasma process is performed. After the plasma process, while still maintaining plasma conditions, the wafer is cooled to a removal temperature and removed from the reaction chamber.

Abstract: An ALD method deposits conformal tantalum-containing material layers on small features of a substrate surface. The method includes the following principal operations: depositing a thin conformal and saturated layer of tantalum-containing precursor over some or all of the substrate surface; using an inert gas or hydrogen plasma to purge the halogen byproducts and unused reactants; reducing the precursor to convert it to a conformal layer of tantalum or tantalum-containing material; using another purge of inert gas or hydrogen plasma to remove the halogen byproducts and unused reactants; and repeating the deposition/reduction cycles until a desired tantalum-containing material layer is achieved. An optional step of treating each newly formed surface of tantalum containing material with a nitrogen-containing agent can be added to create varying amounts of tantalum nitride.

Abstract: A method of forming a multiple-thickness semiconductor-on-insulator, comprising the following steps. A wafer is provided comprising a semiconductor film (having at least two regions) overlying a buried insulator layer overlying a substrate. The semiconductor film within one of the at least two regions is masked to provide at least one semiconductor film masked portion having a first thickness, leaving exposed the semiconductor film within at least one of the at least two regions to provide at least one semiconductor film exposed portion having the first thickness. In one embodiment, at least a portion of the at least one exposed semiconductor film portion is oxidized to provide at least one partially oxidized, exposed semiconductor film portion. Then the oxidized portion of the exposed semiconductor film is removed to leave a portion of the semiconductor film having a second thickness less than the first thickness.

Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.

Abstract: A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity for boron, such as TiN. The capping layer (118) serves as a boron trap that reduces the interface boron concentration for PMOS transistors without reducing the interface arsenic concentration for NMOS transistors.

Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: A method of fabricating a polysilicon film by an excimer laser crystallization process. First, a substrate comprising a first region and a second region is provided. An amorphous silicon layer and a mask layer are formed on the substrate in sequence. Then, a photo-etching process is performed to remove the mask layer in the first region. A heat-retaining capping layer is formed on the mask layer and the amorphous silicon layer. After that, an excimer laser crystallization process is performed so that the amorphous silicon layer in the first region is crystallized into a polysilicon film.

Abstract: A bump formation method and a bump forming apparatus for a semiconductor wafer are provided in which productivity when bumps are formed onto the semiconductor wafer is improved as compared with the conventional art. There are provided a bump forming head, a recognition device, and a control device. ICs formed on the semiconductor wafer are divided into basic blocks. Bump formation is performed continuously for the ICs included in one basic block. Positional recognition for the other basic blocks is performed only when the bump formation operation is shifted from one basic block to another basic block. Thus, in comparison with the conventional art whereby a positional recognition operation is performed every time bumps are formed on each IC, the number of times of performing positional recognition is greatly reduced, so that productivity can be improved.

Abstract: The present invention describes the use of polybenzoxazoles (PBOs) for adhesively bonding articles or materials, especially components used in the semiconductor industry, such as chips and wafers, a process for adhesively bonding materials, especially chips and wafers, chip and/or wafer stacks produced by the process, and adhesive compositions which comprise the polybenzoxazoles of the formula (I).

Abstract: Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.

Abstract: A planarization method includes providing a second and/or third Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes an oxidizing gas.

Abstract: The invention relates to a method for producing a contact substrate (10) as well as to a contact substrate with through-plating between a connector arrangement (21) arranged at the top of a dielectric carrier substrate (12) and the underside of the carrier substrate, wherein the connector arrangement extends along an aperture margin (22) of a substrate recess (15), and the underside (11) of the carrier substrate (12) is supported by a backstop (23), wherein a formed solder material part (24) is placed in the substrate recess (15), and in a subsequent method-related step said formed solder material part (24) is deformed within the substrate recess so as to form a formed contact part (50), such that radial displacement of the material of the formed solder material part in the substrate recess results in a non-positive connection between an intrados surface (28) of the substrate recess and the connector arrangement (21), and that the formed contact part provides through-plating between the connector arrangement

Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench.

Abstract: In a wafer having an LD structure 251 formed on a GaN-based substrate 250, cleavage guide grooves 252 are formed in its surface by scribing from above the LD structure 251 with a diamond needle. The cleavage guide grooves 252 are formed one along each of stripe-shaped waveguides 253 formed parallel to the <1-100> direction of the wafer, and are formed in the shape of broken lines in the <11-20> direction of the wafer.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include depositing an organic anti-reflective coating on the gate material and forming a gate mask on the organic anti-reflective coating. The organic anti-reflective coating around the gate mask may be removed, and the gate material around the gate mask may be removed to define a gate.

Abstract: Wire bonding is performed efficiently by pressing circumference end of a block of a conductive foil by a clamper, and by performing wire bonding of a circuit element of a mounting portion in the block and the conductive pattern in a lump. At a time of wire bonding, oxidation of the conductive foil is prevented by blowing nitrogen gas to the conductive foil from paths and provided at the clamper.

Abstract: A liquid crystal display device includes a substrate, an organic insulating film formed on the substrate, an alignment film having a first etch rate formed on the organic insulating film, and a silicon nitride layer having a second etch rate formed between the alignment film and the organic insulating film, wherein the first etch rate is different from the second etch rate.