Abstract: Machine automated techniques are described for a method of data processing called Relationships Processing. A computing system is disclosed which provides for the high speed recording and extraction of data objects (entities) and for the development of data representing a queried relationship between the entities. Furthermore, methods and systems are disclosed to detect mandatory relations violation between entities by examining whether certain relations exist. The system is expandable to handle the relatively voluminous data bases of large commercial data repositories. A user defines a set of entities and allowed relationships between the entities. The user can expand this set of allowed entities and relationships at any time during the life of the system without reprogramming or compiling of computer program code or disrupting concurrent operational use of the system. Large systems can now be built that are no longer limited to the scope of design requirements known during initial system development.

Abstract: A parallel processor computer system. The computer includes parallel processor units, an instruction unit which provides instructions to the processors and generates input and output address offsets, an invariant address unit which combines a multiconnect pointer with the address offsets to generate input and output operand addresses, and a multiconnect storage unit. Storage elements in the multiconnect unit are arranged in a matrix such that an output operand from a processor is stored in all the elements of an associated row and an input operand for a processor is obtained from any element of an associated column.

Abstract: A system for balancing the loads on channel paths in a digital computer during long running applications is disclosed. Only the load associated with relatively long running applications is monitored. For each volume of data eligible for processing, the selection of volumes is first made from those having affinity to the calling host. The load across the respective connected channel paths is calculated. The calculation is weighted to account for the different magnitudes of load resulting from different applications and to prefer the selection of volumes connected to the fewest unused channel paths such that processing of the selected volume will maintain the maximum number of unused channel paths. The optimal volume is selected as the next volume to be processed. The monitored load on each channel path is then updated to include the load associated with the newly selected volume, assuming that the load associated with processing the volume is distributed evenly across the respective connected channel paths.

Abstract: When a data processing instruction is given to a microprocessor, and the code of a data register subject to designation is held in an instruction register, a first logic level is outputted from the instruction code decoder, but when the register subject to designation is the instruction queuing register in which a subsequent instruction code is to be held, a second logic level is outputted from the instruction code decoder. By the operation of logic switching means, when the first logic level is being outputted, the register select code decoder can select the data register designated, while when the second logic level is being outputted, the register select code decoder can select the instruction queuing register designated. Accordingly, this eliminates the necessity of carrying out the designation of a data register or queuing register in the microprogram, thus making it possible to reduce the size of the microprogram used.

Abstract: An n-bit address selecting instruction read from a program ROM encludes a control bit part and an nm-bit (m<n) operand part. Data used for address selection is stored in k (k.ltoreq.m) extra bit positions of the control bit part. The data stored in the control bit part is supplied to a control bit data detecting circuit. The detecting circuit is responsive to the control bit data in the control bit part to produce first and second control signals. Detecting an address selecting instruction, the detecting circuit produces the first control signal so that a first data entry gate is enabled. When the first data entry gate is enabled, address selecting data stored in the operand part included in the address selecting instruction is written into an m-bit address counter. When the detecting circuit detects the address selecting instruction and that the number of bits of an address to be selected is "m+1" bits or more, the second control signal enables a second data entry gate.