Patents Examined by Mark A Giardino, Jr.
  • Patent number: 11994990
    Abstract: A cache memory having a memory media device row activation-biased caching policy is described. The cache policies that are biased based on row activation counts include at least one of a cache line eviction policy which determines which cache lines are the most evictable from the cache memory, and cache line storage policy which determined which row data is allocated cache lines for storage. A memory controller including a row activation-biased cache memory is also described. The memory media device may be DRAM.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Edmund Gieske, Cagdas Dirik
  • Patent number: 11995340
    Abstract: A read-disturb-based read temperature information access system includes a read-disturb-based read temperature information management subsystem coupled to a plurality of storage devices that each include a read-disturb-based read temperature information Application Programming Interface (API). Each storage device generates and stores read-disturb-based read temperature information associated with that storage device, and when a read-disturb-based read temperature information command is received from the read-disturb-based read temperature information management subsystem that conforms to the read-disturb-based read temperature information API, the storage device receiving that read-disturb-based read temperature information command will execute it to perform at least one operation using the read-disturb-based read temperature information associated with and stored by that storage device.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: May 28, 2024
    Assignee: Dell Products L.P.
    Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson, James Ulery
  • Patent number: 11995328
    Abstract: Implementations described herein relate to memory devices including a single-level cell (SLC) block storing data for migration to multiple multi-level cell (MLC) blocks. In some implementations, a memory device includes multiple MLC blocks that include MLCs, with each MLC being capable of storing at least four bits of data, and multiple SLC blocks that can store data prior to the data being written to one of the MLC blocks. Each SLC block may be capable of storing different data sets that are destined for storage in different MLC blocks. The memory device may include a mapping component that can store a mapping table that includes multiple entries, in which an entry indicates a mapping between a memory location in the SLC blocks and a corresponding MLC block for which data stored in the memory location is destined. Numerous other implementations are described.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Johnny Au Lam, Nathaniel Wessel
  • Patent number: 11995338
    Abstract: A system includes a memory device having a plurality of data blocks and a processing device, the processing device to perform operations identifying an erase operation being performed on a first portion of a plurality of data blocks. The operations further include determining a first rate of performance of the erase operation being performed on the first portion of the plurality of data blocks, identifying a write operation being performed on a second portion of the plurality of data blocks, and determining a second rate of performance of the write operation being performed on the second portion of the plurality of data blocks. The operations further include determining whether the second rate of performance corresponds to the first rate of performance and responsive to the second rate of performance not corresponding to the first rate of performance, adjusting the second rate of performance.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Yang Zhang
  • Patent number: 11989417
    Abstract: A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: May 21, 2024
    Assignee: NXP USA, Inc.
    Inventors: Jon Scott Choy, Timothy Strauss, Maurits Mario Nicolaas Storms, Christopher Nelson Hume, Silvia Wagemans
  • Patent number: 11989435
    Abstract: A flash memory device is re-partitioned over-the-air. A software component responsible for re-partitioning is received. The software component then generates a re-partitioning control structure in the flash memory device and executes re-partitioning steps. The executed re-partitioning steps and currently valid locations of data that needs to be moved in the flash memory device during re-partitioning are recorded in the re-partitioning control structure.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: May 21, 2024
    Assignee: Elektrobit Automotive GmbH
    Inventor: Uwe Hildebrand
  • Patent number: 11989441
    Abstract: A read-disturb-based read temperature identification system includes storage device(s) that each determine read disturb information for each block in that storage device, use that read disturb information to identify a subset of rows in at least one block in that storage device that have a higher read temperature than the other rows in the at least one block in that storage device and, based on that identification, generate and store a local logical storage element read temperature map that identifies a subset of logical storage elements associated with that storage device that have a higher read temperature than the other logical storage elements associated with that storage device. A global read temperature identification subsystem coupled to the storage device(s) may then retrieve at least a portion of the local logical storage element read temperature map(s) and use them to generate a global logical storage element read temperature map.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: May 21, 2024
    Assignee: Dell Products L.P.
    Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson
  • Patent number: 11977769
    Abstract: A memory controller may calculate a sum of a first number of entries stored in a read buffer and a second number of entries stored in a write buffer. If the sum is less than a first threshold and the read/write buffer is not full of entries, then the memory controller can request read/write commands from a host computing device. If the sum is not less than the first threshold or the read/write buffer is full of entries, then the memory controller can assert backpressure to stop the incoming flow newly incoming read/write commands from the host computing device. Additionally, or alternatively, the memory controller may dequeue a write command entry only if a number of write command entries stored in a write command FIFO memory is greater than a second threshold.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Nicola Del Gatto
  • Patent number: 11977783
    Abstract: A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first duplicate command, for duplicating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; and writing the first data at the first destination logical address.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: May 7, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Tzu-Yi Yang
  • Patent number: 11972138
    Abstract: A data handling device includes a plurality of data storage units that are adapted for long term redundant storage of data, generate heat during operation, and are mounted in a manner allowing cooling, and data accessing circuitry adapted determine information chunks relating to data to be stored such that a subset of the information chunks suffice for reproduction of the data, select several of the plurality of data storage units, write the information chunks onto the selected data storage units, determine from which of the selected data storage units to retrieve information chunks based on temperatures of the data storage units to reproduce the data, where at least some of the subset of data storage units are mounted to be cooled by a common vertical air.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: April 30, 2024
    Inventors: Bhupinder Singh Bhullar, John Douglas Fortune
  • Patent number: 11966592
    Abstract: Embodiments are directed to in-place erasure code transcoding for distributed file systems. A file system may be divided into a first partition associated with a first erasure code and a second partition second partition is associated with a second erasure code. If the second partition has sufficient storage space to store protection groups further actions may be performed, including: determining block stores in the first partition associated with the protection groups; transcoding contents of the block stores into other block stores based on the second erasure code; storing the other block stores in the second partition; deleting the block stores from the first partition; shifting another portion of the storage space from the first partition to the second partition such that the shifted other portion increases a size of the second partition to provide sufficient storage space for other protection groups; or the like.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: April 23, 2024
    Assignee: Qumulo, Inc.
    Inventor: Yuxi Bai
  • Patent number: 11966619
    Abstract: An apparatus for executing a software program, comprising at least one hardware processor configured for: identifying in a plurality of computer instructions at least one remote memory access instruction and a following instruction following the at least one remote memory access instruction; executing after the at least one remote memory access instruction a sequence of other instructions, where the sequence of other instructions comprises a return instruction to execute the following instruction; and executing the following instruction; wherein executing the sequence of other instructions comprises executing an updated plurality of computer instructions produced by at least one of: inserting into the plurality of computer instructions the sequence of other instructions or at least one flow-control instruction to execute the sequence of other instructions; and replacing the at least one remote memory access instruction with at least one non-blocking memory access instruction.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: April 23, 2024
    Assignee: Next Silicon Ltd
    Inventors: Elad Raz, Yaron Dinkin
  • Patent number: 11960767
    Abstract: A method includes receiving, by a data storage device, a read command. The method further includes reading a first set of outer code stored to a magnetic recording medium of the data storage device and storing the first set of outer code to memory. The method further includes receiving a write command to write data to the magnetic recording medium and writing a second set of outer code to the magnetic recording medium in connection with the write command.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Seagate Technology LLC
    Inventors: Ryan P. McCallister, Ara Patapoutian, Mark A. Gaertner, Ian Davies
  • Patent number: 11954342
    Abstract: Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Wolfgang Anton Spirkl, Phillip A. Rasmussen, Thomas Hein
  • Patent number: 11954349
    Abstract: The embodiments of the present disclosure relate to a memory system and operating method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks each including a plurality of pages, and ii) a memory controller configured to monitor a program operation on a first super memory block among a plurality of super memory blocks each including at least one of the plurality of memory blocks, and execute a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for a preset time period from a preset reference time point.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 9, 2024
    Assignee: SK hynix Inc.
    Inventor: Young Soo Lim
  • Patent number: 11947816
    Abstract: A method performed by a controller of a solid-state drive (SSD) comprising receiving a command from a host, the command identifying a namespace in a non-volatile semiconductor memory device of the SSD to be formatted, identifying a plurality of regions in the non-volatile semiconductor memory device corresponding to the namespace, unmapping a dummy region in a volatile semiconductor memory device of the SSD using invalid addresses, and copying the invalidated dummy region to each region of the plurality of regions of the namespace.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: April 2, 2024
    Assignee: Kioxia Corporation
    Inventor: Saswati Das
  • Patent number: 11947838
    Abstract: A computer-implemented method according to one approach includes receiving requests to perform data operations on a first storage container, where the data operations include a read operation and a write operation. It is determined whether first data stored on the first storage container is set to a read-only status. In response to determining that the first data is set to the read-only status, the read operation is allowed to be performed on the first container for reading the first data, and the write operation is performed on a second storage container. Moreover, in response to determining that the first data is set to the read-only status, it is determined whether the read-only status has been withdrawn. In response to determining that the read-only status has been withdrawn, further write operations are allowed to be performed on the first storage container.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Lourie Goodall, Joseph M. Swingler
  • Patent number: 11941251
    Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Yoshihisa Kojima, Masanobu Shirakawa, Kiyotaka Iwasaki
  • Patent number: 11934688
    Abstract: Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Robert B. Eisenhuth
  • Patent number: 11934692
    Abstract: Methods, systems, and devices for write booster buffer and hibernate are described. The memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. In some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Deping He