Abstract: A storage controller for controlling a nonvolatile memory device is disclosed. The storage controller includes a buffer memory and a processor. The processor is configured to provide a plurality of physical functions having equivalent authorities to a host, and to allocate, in response to a resource allocation request received from the host via an arbitrary physical function among the plurality of physical functions, a namespace provided by the nonvolatile memory device and a buffer region included in the buffer memory to one or more target physical functions among the plurality of physical functions.

Abstract: A storage device includes: a memory device; and a memory controller configured to receive, from an external device having an external memory, a write command for storing data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire write data from the external device based on the address information. The memory controller may be further configured to store the write data in the memory device in response to the write command. The memory controller may be further configured to acquire a portion of the write data from the external memory upon a failure of storage of the portion of the write data in the memory device, and provide a response to the write command to the external device after completing storing of the write data in the memory device.

Abstract: A memory system includes a non-volatile memory including a plurality of memory cells; and a controller. The controller is configured to perform a multi-step write operation to write multi-bit data with respect to each of target memory cells through a first programming to set a first threshold voltage and then a second programming to set a second threshold voltage. The controller, during the multi-step write operation, determines a time period elapsed from a first time at which the first programming with respect to a first memory cell of the target memory cells has been performed, and varies a second time at which the second programming with respect to the first memory cell is performed based on whether the time period is greater than a first threshold.

Abstract: Solutions for managing RAID virtual disks. Some solutions enable increased use of hardware circuitry to schedule and perform IO on a virtual drive, providing for more efficient IO. In some cases, this can be accomplished by notifying the hardware of precise regions of a virtual disk affected by the maintenance operation and any given time. The hardware then, can continue to perform host IO on portions of the logical disk not undergoing maintenance.

Abstract: A storage device may maintain persistent data after converting from firmware associated with a first mode to firmware associated with a second mode. The device receives a firmware package associated with the second mode, determines when the package includes a descriptor, and executes a copy macro in the descriptor to translate a first data structure used in the first mode to the second data structure used in the second mode. When the device receives a commit command and determines that the second data structure is in a volatile memory, the device copies the second data structure to a non-volatile memory. After completing the commit command and power cycling, when the device is being formatted in the second mode, the device reads the second data structure from the non-volatile memory, transfers the second data structure to a persistence module, and formats in the second mode.

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a plurality of read command sequences configured to instruct a rewritable non-volatile memory module to read a first physical unit by using a plurality of read voltage levels; after the read command sequences are sent, receiving first data from the rewritable non-volatile memory module, where the first data includes replacement data corresponding to a plurality of first bits reflecting a read result of a first memory cell by using the read voltage levels, and a data amount of the first data is less than a total data amount of the first bits; after the first data is received, performing data restoration on the first data to obtain a plurality of second bits; performing a decoding operation according to the second bits.

Abstract: Techniques are provided for journal replay optimization. A distributed storage architecture can implement a journal within memory for logging write operations into log records. Latency of executing the write operations is improved because the write operations can be responded back to clients as complete once logged within the journal without having to store the data to higher latency disk storage. If there is a failure, then a replay process is performed to replay the write operations logged within the journal in order to bring a file system up-to-date. The time to complete the replay of the write operations is significantly reduced by caching metadata (e.g., indirect blocks, checksums, buftree identifiers, file block numbers, and consistency point counts) directly into log records. Replay can quickly access this metadata for replaying the write operations because the metadata does not need to be retrieved from the higher latency disk storage into memory.

Abstract: An illustrative method includes a controller associated with a plurality of clusters receiving, from a user, a disaster recovery policy of a containerized application deployed on a first cluster in the plurality of clusters, determining a cluster profile of each second cluster among one or more second clusters that are distinct from the first cluster in the plurality of clusters, identifying, from the one or more second clusters, a particular cluster based on the disaster recovery policy of the containerized application and the cluster profile of each second cluster, and assigning the particular cluster to be a disaster recovery cluster for the containerized application.

Abstract: A method for controlling aggregation for HRAM comprises a processing device, using a buffer manager, to receive instructions that include smaller-sized block write instructions from a host system. The processing device, using an aggregation engine, aggregates the smaller-sized block write instructions from the buffer manager into a plurality of larger-sized write instructions. The processing device issues a burst write instruction comprising the larger-sized write instructions to the memory component via the interface. The memory component can be HRAM and the interface can be a modified DDR-L5 interface for HRAM. Other embodiments are described herein.

Abstract: A method, computer program product, and computing system for generating a plurality of artificial storage devices for a storage system, wherein each artificial storage device includes a defined storage capacity. A total useable storage capacity for the storage system is defined based upon, at least in part, the defined storage capacity for each artificial storage device and a storage capacity associated with a plurality of physical storage devices. One or more input/output (IO) requests are processed on the storage system. An IO request concerning an artificial storage device of the plurality of artificial storage devices is discarded.

Abstract: Disclosed herein are a dynamic memory management apparatus and a method for allocating/deallocating dynamic memory. The apparatus includes actual memory configured to allocate or deallocate a heap, virtual memory configured to set/store heap allocation information at a virtual address mapped to an actual address that is a body start address of a heap area of the actual memory, and a dynamic memory manager configured to process a memory allocation or deallocation request and the virtual memory, wherein the heap allocation information includes access authority information for storing information indicating whether a heap at an actual address is allocated or deallocated, and count information increased whenever a heap is allocated, and the dynamic memory manager is configured to return an address pointer including an actual address of a heap allocated to the actual memory and heap allocation information to the program, and process a heap deallocation or reallocation request.

Abstract: A storage device may dynamically allocate, to a buffer, at least one among M number of buffer units each capable of storing at least one of a plurality of L2P mapping units. When receiving, from an external device, a mapping unit command requesting one or more target L2P mapping units among the plurality of L2P mapping units, the storage device may store the target L2P mapping units in the buffer before transmitting the target L2P mapping units to the external device.

Abstract: A semiconductor storage apparatus having a function of emulating an erasing operation of a flash memory is provided. A resistive random access memory of the disclosure includes: a memory cell array; a controller that reads or writes the memory cell array according to an input of command; an erasing command allowance register that sets whether or not to receive an erasing command; and a busy time adjustment register that adjusts a busy time. In a case of setting to allow a reception of the erasing command, the controller responds to an input of the erasing command to emulate the erasing operation, and specifies busy information including the busy time adjusted by the busy time adjustment register.

Abstract: A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.

Abstract: Embodiments of the present disclosure provide a method, apparatus, electronic device and storage medium for storing data. After target data is obtained, a first data feature of the target data is extracted, the first data feature representing a data volume of the target data; the target shard number is obtained based on the first data feature, the target shard number representing the number of storage units for storing target data; a corresponding storage engine is obtained based on the target shard number, and the target data is stored in the storage engines in shards. The matched target shard number is obtained based on the first data feature of the target data, and a corresponding storage engine for storage is obtained based on the target shard number.

Abstract: A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

Abstract: A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.

Abstract: Disclosed is a write method comprising a step in which a storage device determines an execution order between received first and second write commands, and executes the first write command and the second write command according to the determined execution order. The first write command comprises first stream identification information having {first stream ID, first epoch ID}, the second write command comprises second stream identification information having {second stream ID, second epoch ID}, and when the first stream ID and the second stream ID are different from each other, the execution order is determined without using the result of comparison between the first epoch ID and the second epoch ID.

Abstract: In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory cell selected for data sanitation, prior to applying a programming pulse to the corresponding word line, a soft erase operation is performed. After biasing the memory cells and select gates of the NAND strings to a low voltage, a soft erase voltage pulse is applied to the source lines and bit line to pre-charge the NAND string channels with holes.

Abstract: A method and an apparatus for generating information based on a FIFO memory, a device and a medium. In the method, a write credit score and a read credit score of a current FIFO memory are determined by a total capacity of the FIFO memory, and a read address, a write address, a read data enable signal value and a write data enable signal value of the current FIFO memory; and the write credit score represents the number of data sets that can be written into the FIFO memory normally; and the read credit score represents the number of data sets that can be read from the FIFO memory normally; and after sending the write credit score and the read credit score to a preceding-stage device, the preceding-stage device read and write data according to the write credit score and the read credit score.