Patents Examined by Mark A Giardino, Jr.
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Patent number: 12204768Abstract: A set of blocks of a storage device are allocated for storage of data, wherein the set of blocks of the storage device is selected based on a power requirement that is based on a number of partially programmed blocks stored in the cache. Subsequent data to be stored at the storage device is assigned to the set of blocks for storage at the storage device.Type: GrantFiled: May 26, 2023Date of Patent: January 21, 2025Assignee: PURE STORAGE, INC.Inventors: Andrew R. Bernat, Wei Tang
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Patent number: 12197738Abstract: The present disclosure describes aspects of health management for magnetic storage media. In some aspects, a media health manager determines, with a read channel, read metrics for a sector of magnetic storage media that resides in a zone of magnetic storage media. The media health manager accesses read metrics of the zone and updates the read metrics of the zone based on the read metrics determined for the sector to provide updated read metrics for the zone of magnetic storage media. A health score for the zone of magnetic storage media is then determined with a neural network based on the updated read metrics of the zone of magnetic storage media. By so doing, gradual wear of the magnetic storage media may be predicted using the health score, enabling replacement of a magnetic storage media device before failure to improve reliability or availability of data stored to the device.Type: GrantFiled: September 19, 2022Date of Patent: January 14, 2025Assignee: Marvell Asia Pte, Ltd.Inventor: Nitin Nangare
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Patent number: 12197747Abstract: A logic simulation device according to an aspect of the present disclosure includes an operation model of a resistance-change memory element. The resistance-change memory element is provided between two terminals. The operation model includes a register section for holding data, a truth table, and a determining section. The truth table defines a relationship between signal values of the two terminals, and data writing to the register section and data reading from the register section. The determining section performs determination about the data writing and the data reading on the basis of signal values inputted to the two terminals and the truth table.Type: GrantFiled: August 4, 2021Date of Patent: January 14, 2025Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Haruko Takahashi, Masami Kuroda, Midori Aizawa
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Patent number: 12197335Abstract: Prefetch circuitry may be configured to transmit a message to cancel a prefetch of one or more cache blocks of a group. The message may correspond to a prefetch message by indicating an address for the group and a bit field for the one or more cache blocks of the group to cancel. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.Type: GrantFiled: March 13, 2023Date of Patent: January 14, 2025Assignee: SiFive, Inc.Inventors: Eric Andrew Gouldey, Wesley Waylon Terpstra, Michael Klinglesmith
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Patent number: 12182411Abstract: A semiconductor storage device includes a plurality of semiconductor memory chips and a bridge chip. The bridge chip includes a first interface connectable to an external memory controller that is external to the semiconductor storage device, a plurality of second interfaces connected to the semiconductor memory chips, and a controller. The controller is configured to, upon receiving, by the first interface, a first command sequence that includes a data transfer command to perform data transfer with one of the semiconductor chips and size information indicating a size of data to be transferred, start an operation to perform the data transfer, and end the operation, upon an amount of data that has been received by the first interface during the data transfer reaching the size indicated by the size information.Type: GrantFiled: February 28, 2023Date of Patent: December 31, 2024Assignee: Kioxia CorporationInventor: Goichi Ootomo
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Patent number: 12182443Abstract: The present disclosure relates to a data storage method and apparatus, a non-transitory computer-readable medium, and an electronic device. In the method, when data to be stored that is sent by a container is received through a target interface, a first buffer is generated in storage space of a kernel, and a target length, in the first buffer, of the data to be stored and a start address, in the first buffer, of the data to be stored are obtained. A target physical address in the kernel corresponding to the data to be stored is determined based on the target length and the start address. The target physical address is mapped to a target virtual address in a storage service module.Type: GrantFiled: May 24, 2024Date of Patent: December 31, 2024Assignee: Beijing Bytedance Network Technology Co., Ltd.Inventors: Yongji Xie, Qi Liu, Xiongchun Duan, Jiachen Zhang, Wen Chai, Yu Zhang, Jian Wang
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Patent number: 12166822Abstract: A method for execution by one or more computing devices of a storage network includes obtaining performance impact information regarding a data reconstruction operation associated with a computing device of the one or more computing devices, where the data reconstruction operation is regarding reconstructing data at a first reconstruction rate of a plurality of reconstruction rates, and where the performance impact information includes performance metrics of the storage network affected by the data reconstruction operation. The method further includes determining a second reconstruction rate of the plurality of reconstruction rates to utilize for the data reconstruction operation based on the performance impact information to achieve a first performance metric of the performance metrics. The method further includes executing the data reconstruction operation in accordance with the second reconstruction rate.Type: GrantFiled: February 15, 2023Date of Patent: December 10, 2024Assignee: Pure Storage, Inc.Inventors: Ravi V. Khadiwala, Asimuddin Kazi
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Patent number: 12153808Abstract: A memory device includes a row decoder that receives one or more normal addresses and one or more control addresses, and a memory cell array connected to the row decoder via a plurality of word lines. In a normal operation, in response to receiving the one or more normal addresses, any one word line among the plurality of word lines is enabled. In an initialization operation, in response to receiving the one or more normal addresses and the one or more control addresses, at least two word lines among the plurality of word lines are enabled. Data of memory cells of the memory cell array connected to the enabled at least two word lines is initialized.Type: GrantFiled: December 29, 2022Date of Patent: November 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiwoong Kim, Moonki Jang, Yunhwan Kim, Myeongwhan Hyun
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Patent number: 12147525Abstract: The present disclosure relates to methods and systems for evaluating a storage medium. The method may include receiving, via a user interface of a host, a user request to evaluate a storage medium coupled to a first controller. The method may also include determining whether there is a first binding history table associated with the storage medium stored in the host. In response to a determination that there is no first binding history table stored in the host, the method may include retrieving a binding history table from the storage medium via the first controller and determining the storage medium as a second-hand storage medium if there is at least one second controller different from the first controller in the binding history table.Type: GrantFiled: April 25, 2023Date of Patent: November 19, 2024Assignee: INNOGRIT TECHNOLOGIES CO., LTD.Inventors: Moyang Chen, Zining Wu
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Patent number: 12147664Abstract: A system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a correlation component that, based on performance data, such as current performance data and/or historical performance data, for an application stored at a storage system, correlates a performance category with the application, and an execution component that, based on the performance category correlated to the application, executes a modification at the storage system, wherein the modification at the storage system comprises changing a functioning of the storage system relative to the application. In an embodiment, the data comprised by the application can be maintained in a non-accessed state to execute the modification at the storage system.Type: GrantFiled: December 23, 2022Date of Patent: November 19, 2024Assignee: NETAPP, INC.Inventors: Nathanael Black, Ashwin Palani, Jeffrey MacFarland
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Patent number: 12147315Abstract: A system identifies an intent policy model associated with an initial time. The system updates a data structure to cause the data structure to include one or more portions. Each portion of the data structure is associated with a start time and an end time. Each portion includes: a first delta snapshot that indicates one or more first changes to the intent policy model from the initial time to the start time associated with the portion, and one or more additional delta snapshots that respectively indicate one or more incremental changes to the intent policy model at times from the start time and to the end time associated with the portion of the data structure.Type: GrantFiled: November 29, 2022Date of Patent: November 19, 2024Assignee: Juniper Networks, Inc.Inventors: Chandrasekhar A, Premchandar N, Jayanthi R
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Patent number: 12141069Abstract: A data processing apparatus is provided. Prefetch circuitry generates a prefetch request for a cache line prior to the cache line being explicitly requested. The cache line is predicted to be required for a store operation in the future. Issuing circuitry issues the prefetch request to a memory hierarchy and filter circuitry filters the prefetch request based on at least one other prefetch request made to the cache line, to control whether the prefetch request is issued by the issuing circuitry.Type: GrantFiled: December 28, 2022Date of Patent: November 12, 2024Assignee: Arm LimitedInventors: Luca Maroncelli, Cedric Denis Robert Airaud, Florent Begon, Peter Raphael Eid
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Patent number: 12112165Abstract: Systems, methods, and apparatus including computer-readable mediums for managing status information of logic units are provided. In one aspect, a device includes a semiconductor device including one or more logic units and a reporting bus and a controller coupled to the semiconductor device and configured to store status information of the one or more logic units in the semiconductor device. Each of the one or more logic units is configured to send information associated with the logic unit using a corresponding reporting unit in the semiconductor device through the reporting bus to the controller to indicate a status of the logic unit. The controller is configured to, in response to receiving the information associated with the logic unit, update corresponding status information of the logic unit based on the status of the logic unit.Type: GrantFiled: September 29, 2022Date of Patent: October 8, 2024Assignee: Macronix International Co., Ltd.Inventors: Sheng-Lun Wu, Chun-Lien Su
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Patent number: 12093143Abstract: A method for execution by a distributed storage network begins by receiving a request to transfer a copy of a set of encoded data slices from at least some associated virtual storage vaults to a destination virtual storage vault and continues by determining whether the destination storage unit supports a source virtual storage vault of the at least some source virtual storage vaults. When the destination storage unit supports the source virtual storage vault the method continues by determining a sub-set of encoded data slices of the set of encoded data slices for transfer and finally, by facilitating sending the sub-set of encoded data slices to the destination storage unit.Type: GrantFiled: March 10, 2023Date of Patent: September 17, 2024Assignee: Pure Storage, Inc.Inventors: Adam M. Gray, Greg R. Dhuse, Andrew D. Baptist, Ravi V. Khadiwala, Wesley B. Leggette, Scott M. Horan, Franco V. Borich, Bart R. Cilfone, Daniel J. Scholl
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Patent number: 12086473Abstract: Copying data using references to the data, including: receiving a request to write the source data to a target volume, wherein the request to write the source data indicates the reference information; obtaining a metadata representation of the source data using the reference information; an copying, using the reference information, the metadata representation of the source data to the target volume.Type: GrantFiled: April 20, 2023Date of Patent: September 10, 2024Assignee: PURE STORAGE, INC.Inventors: Roland Dreier, Rachel Shanava, Krishna Kant
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Patent number: 12086454Abstract: A data processing system includes an external memory system, a processor and an internal memory system. The internal memory system includes an internal memory that stores data for use by the processor when performing data processing operations. The internal memory system also includes a data encoder associated with the internal memory. The data encoder reads data from the external memory system to the data encoder and returns the data to the external memory system from the data encoder, without storing the data in the internal memory.Type: GrantFiled: November 18, 2021Date of Patent: September 10, 2024Assignee: Arm LimitedInventors: Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt
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Patent number: 12086467Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.Type: GrantFiled: February 28, 2023Date of Patent: September 10, 2024Assignee: Macronix International Co., Ltd.Inventors: Ting-Yu Liu, Yi-Chun Liu
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Patent number: 12079491Abstract: A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.Type: GrantFiled: January 5, 2023Date of Patent: September 3, 2024Assignees: Samsung Electronics Co., Ltd., Dongguk University Industry-Academic Cooperation FoundationInventors: Taewoo Han, Wooil Kim, Taehun Kim
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Patent number: 12073090Abstract: A system comprising a row hammer mitigation circuitry and a cache memory that collaborate to mitigate row hammer attacks on a memory media device is described. The cache memory biases cache policy based on row access count information maintained by the row hammer mitigation circuit. The row hammer mitigation circuitry may be implemented in a memory controller. The memory media device may be DRAM. Corresponding methods are also described.Type: GrantFiled: September 9, 2022Date of Patent: August 27, 2024Assignee: Micron Technology, Inc.Inventors: Edmund Gieske, Cagdas Dirik
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Patent number: 12050806Abstract: A distributed data storage system using erasure coding (EC) provides advantages of EC data storage while retaining high resiliency for EC data storage architectures having fewer data storage nodes than the number of EC data-plus-parity fragments. An illustrative embodiment is a three-node data storage system with EC 4+2. Incoming data is temporarily replicated to ameliorate the effects of certain storage node outages or fatal disk failures, so that read and write operations can continue from/to the storage system. The system is equipped to automatically heal failed EC write attempts in a manner transparent to users and/or applications: when all storage nodes are operational, the distributed data storage system automatically converts the temporarily replicated data to EC storage and reclaims storage space previously used by the temporarily replicated data. Individual hardware failures are healed through migration techniques that reconstruct and re-fragment data blocks according to the governing EC scheme.Type: GrantFiled: February 21, 2023Date of Patent: July 30, 2024Assignee: Commvault Systems, Inc.Inventors: Anand Vishwanath Vastrad, Avinash Lakshman, Suhani Gupta, Srinivas Lakshman