Abstract: Disclosed herein are a dynamic memory management apparatus and a method for allocating/deallocating dynamic memory. The apparatus includes actual memory configured to allocate or deallocate a heap, virtual memory configured to set/store heap allocation information at a virtual address mapped to an actual address that is a body start address of a heap area of the actual memory, and a dynamic memory manager configured to process a memory allocation or deallocation request and the virtual memory, wherein the heap allocation information includes access authority information for storing information indicating whether a heap at an actual address is allocated or deallocated, and count information increased whenever a heap is allocated, and the dynamic memory manager is configured to return an address pointer including an actual address of a heap allocated to the actual memory and heap allocation information to the program, and process a heap deallocation or reallocation request.

Abstract: A storage device may dynamically allocate, to a buffer, at least one among M number of buffer units each capable of storing at least one of a plurality of L2P mapping units. When receiving, from an external device, a mapping unit command requesting one or more target L2P mapping units among the plurality of L2P mapping units, the storage device may store the target L2P mapping units in the buffer before transmitting the target L2P mapping units to the external device.

Abstract: A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.

Abstract: A semiconductor storage apparatus having a function of emulating an erasing operation of a flash memory is provided. A resistive random access memory of the disclosure includes: a memory cell array; a controller that reads or writes the memory cell array according to an input of command; an erasing command allowance register that sets whether or not to receive an erasing command; and a busy time adjustment register that adjusts a busy time. In a case of setting to allow a reception of the erasing command, the controller responds to an input of the erasing command to emulate the erasing operation, and specifies busy information including the busy time adjusted by the busy time adjustment register.

Abstract: Embodiments of the present disclosure provide a method, apparatus, electronic device and storage medium for storing data. After target data is obtained, a first data feature of the target data is extracted, the first data feature representing a data volume of the target data; the target shard number is obtained based on the first data feature, the target shard number representing the number of storage units for storing target data; a corresponding storage engine is obtained based on the target shard number, and the target data is stored in the storage engines in shards. The matched target shard number is obtained based on the first data feature of the target data, and a corresponding storage engine for storage is obtained based on the target shard number.

Abstract: A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

Abstract: Disclosed is a write method comprising a step in which a storage device determines an execution order between received first and second write commands, and executes the first write command and the second write command according to the determined execution order. The first write command comprises first stream identification information having {first stream ID, first epoch ID}, the second write command comprises second stream identification information having {second stream ID, second epoch ID}, and when the first stream ID and the second stream ID are different from each other, the execution order is determined without using the result of comparison between the first epoch ID and the second epoch ID.

Abstract: A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.

Abstract: In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory cell selected for data sanitation, prior to applying a programming pulse to the corresponding word line, a soft erase operation is performed. After biasing the memory cells and select gates of the NAND strings to a low voltage, a soft erase voltage pulse is applied to the source lines and bit line to pre-charge the NAND string channels with holes.

Abstract: A method and an apparatus for generating information based on a FIFO memory, a device and a medium. In the method, a write credit score and a read credit score of a current FIFO memory are determined by a total capacity of the FIFO memory, and a read address, a write address, a read data enable signal value and a write data enable signal value of the current FIFO memory; and the write credit score represents the number of data sets that can be written into the FIFO memory normally; and the read credit score represents the number of data sets that can be read from the FIFO memory normally; and after sending the write credit score and the read credit score to a preceding-stage device, the preceding-stage device read and write data according to the write credit score and the read credit score.

Abstract: A storage network operates by: encoding, via a dispersed error encoding, at least one data object as a write threshold number of encoded data slices; storing the write threshold number of the encoded data slices in a set of storage units of the storage network; determining when, due to a failure, less than a pillar width number of the encoded data slices are retrievable from the set of storage units: retrieving a decode threshold number of the encoded data slices from others of the set of storage units; decoding the decode threshold number of the encoded data slices to reproduce the at least one data object; restoring availability of the pillar width number of the encoded data slices of the common revision by: rebuilding at least a subset of encoded data slices of the set of encoded data slices, based on an encoding of the at least one data object; and storing the at least a subset of encoded data slices in the storage network.

Abstract: There are provided systems and methods for a multi-layer cache to prevent user experience interrupts during feature flag management. A service provider may provide applications to computing devices of users including mobile applications. Use and availability of features in an application may be configured using feature flags, however, change of these feature flags may initiate an application refresh that affects user experiences with the application. To prevent interruptions, a multi-layer data cache may be used where feature flag data for the feature flags may initially be loaded, after a time period, to a first layer cache that is not used to update the application. When conditions exist for updating the application without affecting the user experience, such as if the user is no longer using a workflow, the feature flag data may be loaded to a second layer cache. The second layer cache may then be used for updating.

Abstract: A set of blocks of a storage device are allocated for storage of data, wherein the set of blocks of the storage device is selected based on a power requirement that is based on a number of partially programmed blocks stored in the cache. Subsequent data to be stored at the storage device is assigned to the set of blocks for storage at the storage device.

Abstract: The present disclosure describes aspects of health management for magnetic storage media. In some aspects, a media health manager determines, with a read channel, read metrics for a sector of magnetic storage media that resides in a zone of magnetic storage media. The media health manager accesses read metrics of the zone and updates the read metrics of the zone based on the read metrics determined for the sector to provide updated read metrics for the zone of magnetic storage media. A health score for the zone of magnetic storage media is then determined with a neural network based on the updated read metrics of the zone of magnetic storage media. By so doing, gradual wear of the magnetic storage media may be predicted using the health score, enabling replacement of a magnetic storage media device before failure to improve reliability or availability of data stored to the device.

Abstract: A logic simulation device according to an aspect of the present disclosure includes an operation model of a resistance-change memory element. The resistance-change memory element is provided between two terminals. The operation model includes a register section for holding data, a truth table, and a determining section. The truth table defines a relationship between signal values of the two terminals, and data writing to the register section and data reading from the register section. The determining section performs determination about the data writing and the data reading on the basis of signal values inputted to the two terminals and the truth table.

Abstract: Prefetch circuitry may be configured to transmit a message to cancel a prefetch of one or more cache blocks of a group. The message may correspond to a prefetch message by indicating an address for the group and a bit field for the one or more cache blocks of the group to cancel. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.

Abstract: The present disclosure relates to a data storage method and apparatus, a non-transitory computer-readable medium, and an electronic device. In the method, when data to be stored that is sent by a container is received through a target interface, a first buffer is generated in storage space of a kernel, and a target length, in the first buffer, of the data to be stored and a start address, in the first buffer, of the data to be stored are obtained. A target physical address in the kernel corresponding to the data to be stored is determined based on the target length and the start address. The target physical address is mapped to a target virtual address in a storage service module.

Abstract: A semiconductor storage device includes a plurality of semiconductor memory chips and a bridge chip. The bridge chip includes a first interface connectable to an external memory controller that is external to the semiconductor storage device, a plurality of second interfaces connected to the semiconductor memory chips, and a controller. The controller is configured to, upon receiving, by the first interface, a first command sequence that includes a data transfer command to perform data transfer with one of the semiconductor chips and size information indicating a size of data to be transferred, start an operation to perform the data transfer, and end the operation, upon an amount of data that has been received by the first interface during the data transfer reaching the size indicated by the size information.

Abstract: A method for execution by one or more computing devices of a storage network includes obtaining performance impact information regarding a data reconstruction operation associated with a computing device of the one or more computing devices, where the data reconstruction operation is regarding reconstructing data at a first reconstruction rate of a plurality of reconstruction rates, and where the performance impact information includes performance metrics of the storage network affected by the data reconstruction operation. The method further includes determining a second reconstruction rate of the plurality of reconstruction rates to utilize for the data reconstruction operation based on the performance impact information to achieve a first performance metric of the performance metrics. The method further includes executing the data reconstruction operation in accordance with the second reconstruction rate.

Abstract: A memory device includes a row decoder that receives one or more normal addresses and one or more control addresses, and a memory cell array connected to the row decoder via a plurality of word lines. In a normal operation, in response to receiving the one or more normal addresses, any one word line among the plurality of word lines is enabled. In an initialization operation, in response to receiving the one or more normal addresses and the one or more control addresses, at least two word lines among the plurality of word lines are enabled. Data of memory cells of the memory cell array connected to the enabled at least two word lines is initialized.