Abstract: A memory image can be captured by generating metadata indicative of a state of volatile memory and/or byte-addressable PMEM at a particular time during execution of a process by an application. This memory image can be persisted without copying the in-memory data into a separate persistent storage by storing the metadata and safekeeping the in-memory data in the volatile memory and/or PMEM. Metadata associated with multiple time-evolved memory images captured can be stored and managed using a linked index scheme. A linked index scheme can be configured in various ways including a full index and a difference-only index. The memory images can be used for various purposes including suspending and later resuming execution of the application process, restoring a failed application to a previous point in time, cloning an application, and recovering an application process to a most recent state in an application log.

Abstract: The present disclosure provides a power-down test method for a firmware of a memory system, a memory system, a computer device, a computer-readable storage medium, and a power-down test system. The disclosed method for testing power-down operations of the firmware of the memory system comprises configuring the firmware by setting a plurality of power-down trigger signal points each associated with a corresponding one of the plurality of preset logic points to be tested, and triggering a plurality of power-down test operations at the plurality of power-down trigger signal points to test the plurality of preset logic points of the firmware.

Abstract: An apparatus comprises a processing device configured to initiate garbage collection for data pages stored in local storage of a storage node of a storage system. The processing device is also configured to determine, for a given data page stored in the local storage of the storage node, a validity score characterizing a size of changed data in the given data page, and to compare the validity score for the given data page to at least one designated threshold. The processing device is further configured to update a given page object for the given data page in an object store of persistent storage responsive to a first comparison result, and to generate, in the object store of the persistent storage, a page delta object for the given data page responsive to a second comparison result, the page delta object comprising the changed data in the given data page.

Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

Abstract: Implementations described herein relate to memory devices including a single-level cell (SLC) block storing data for migration to multiple multi-level cell (MLC) blocks. In some implementations, a memory device includes multiple MLC blocks that include MLCs, with each MLC being capable of storing at least four bits of data, and multiple SLC blocks that can store data prior to the data being written to one of the MLC blocks. Each SLC block may be capable of storing different data sets that are destined for storage in different MLC blocks. The memory device may include a mapping component that can store a mapping table that includes multiple entries, in which an entry indicates a mapping between a memory location in the SLC blocks and a corresponding MLC block for which data stored in the memory location is destined. Numerous other implementations are described.

Abstract: A read-disturb-based read temperature information access system includes a read-disturb-based read temperature information management subsystem coupled to a plurality of storage devices that each include a read-disturb-based read temperature information Application Programming Interface (API). Each storage device generates and stores read-disturb-based read temperature information associated with that storage device, and when a read-disturb-based read temperature information command is received from the read-disturb-based read temperature information management subsystem that conforms to the read-disturb-based read temperature information API, the storage device receiving that read-disturb-based read temperature information command will execute it to perform at least one operation using the read-disturb-based read temperature information associated with and stored by that storage device.

Abstract: A cache memory having a memory media device row activation-biased caching policy is described. The cache policies that are biased based on row activation counts include at least one of a cache line eviction policy which determines which cache lines are the most evictable from the cache memory, and cache line storage policy which determined which row data is allocated cache lines for storage. A memory controller including a row activation-biased cache memory is also described. The memory media device may be DRAM.

Abstract: A system includes a memory device having a plurality of data blocks and a processing device, the processing device to perform operations identifying an erase operation being performed on a first portion of a plurality of data blocks. The operations further include determining a first rate of performance of the erase operation being performed on the first portion of the plurality of data blocks, identifying a write operation being performed on a second portion of the plurality of data blocks, and determining a second rate of performance of the write operation being performed on the second portion of the plurality of data blocks. The operations further include determining whether the second rate of performance corresponds to the first rate of performance and responsive to the second rate of performance not corresponding to the first rate of performance, adjusting the second rate of performance.

Abstract: A flash memory device is re-partitioned over-the-air. A software component responsible for re-partitioning is received. The software component then generates a re-partitioning control structure in the flash memory device and executes re-partitioning steps. The executed re-partitioning steps and currently valid locations of data that needs to be moved in the flash memory device during re-partitioning are recorded in the re-partitioning control structure.

Abstract: A read-disturb-based read temperature identification system includes storage device(s) that each determine read disturb information for each block in that storage device, use that read disturb information to identify a subset of rows in at least one block in that storage device that have a higher read temperature than the other rows in the at least one block in that storage device and, based on that identification, generate and store a local logical storage element read temperature map that identifies a subset of logical storage elements associated with that storage device that have a higher read temperature than the other logical storage elements associated with that storage device. A global read temperature identification subsystem coupled to the storage device(s) may then retrieve at least a portion of the local logical storage element read temperature map(s) and use them to generate a global logical storage element read temperature map.

Abstract: A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.

Abstract: A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first duplicate command, for duplicating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; and writing the first data at the first destination logical address.

Abstract: A memory controller may calculate a sum of a first number of entries stored in a read buffer and a second number of entries stored in a write buffer. If the sum is less than a first threshold and the read/write buffer is not full of entries, then the memory controller can request read/write commands from a host computing device. If the sum is not less than the first threshold or the read/write buffer is full of entries, then the memory controller can assert backpressure to stop the incoming flow newly incoming read/write commands from the host computing device. Additionally, or alternatively, the memory controller may dequeue a write command entry only if a number of write command entries stored in a write command FIFO memory is greater than a second threshold.

Abstract: A data handling device includes a plurality of data storage units that are adapted for long term redundant storage of data, generate heat during operation, and are mounted in a manner allowing cooling, and data accessing circuitry adapted determine information chunks relating to data to be stored such that a subset of the information chunks suffice for reproduction of the data, select several of the plurality of data storage units, write the information chunks onto the selected data storage units, determine from which of the selected data storage units to retrieve information chunks based on temperatures of the data storage units to reproduce the data, where at least some of the subset of data storage units are mounted to be cooled by a common vertical air.

Abstract: An apparatus for executing a software program, comprising at least one hardware processor configured for: identifying in a plurality of computer instructions at least one remote memory access instruction and a following instruction following the at least one remote memory access instruction; executing after the at least one remote memory access instruction a sequence of other instructions, where the sequence of other instructions comprises a return instruction to execute the following instruction; and executing the following instruction; wherein executing the sequence of other instructions comprises executing an updated plurality of computer instructions produced by at least one of: inserting into the plurality of computer instructions the sequence of other instructions or at least one flow-control instruction to execute the sequence of other instructions; and replacing the at least one remote memory access instruction with at least one non-blocking memory access instruction.

Abstract: Embodiments are directed to in-place erasure code transcoding for distributed file systems. A file system may be divided into a first partition associated with a first erasure code and a second partition second partition is associated with a second erasure code. If the second partition has sufficient storage space to store protection groups further actions may be performed, including: determining block stores in the first partition associated with the protection groups; transcoding contents of the block stores into other block stores based on the second erasure code; storing the other block stores in the second partition; deleting the block stores from the first partition; shifting another portion of the storage space from the first partition to the second partition such that the shifted other portion increases a size of the second partition to provide sufficient storage space for other protection groups; or the like.

Abstract: A method includes receiving, by a data storage device, a read command. The method further includes reading a first set of outer code stored to a magnetic recording medium of the data storage device and storing the first set of outer code to memory. The method further includes receiving a write command to write data to the magnetic recording medium and writing a second set of outer code to the magnetic recording medium in connection with the write command.

Abstract: Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.

Abstract: The embodiments of the present disclosure relate to a memory system and operating method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks each including a plurality of pages, and ii) a memory controller configured to monitor a program operation on a first super memory block among a plurality of super memory blocks each including at least one of the plurality of memory blocks, and execute a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for a preset time period from a preset reference time point.