Patents Examined by Mark A Giardino, Jr.
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Patent number: 12153808Abstract: A memory device includes a row decoder that receives one or more normal addresses and one or more control addresses, and a memory cell array connected to the row decoder via a plurality of word lines. In a normal operation, in response to receiving the one or more normal addresses, any one word line among the plurality of word lines is enabled. In an initialization operation, in response to receiving the one or more normal addresses and the one or more control addresses, at least two word lines among the plurality of word lines are enabled. Data of memory cells of the memory cell array connected to the enabled at least two word lines is initialized.Type: GrantFiled: December 29, 2022Date of Patent: November 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiwoong Kim, Moonki Jang, Yunhwan Kim, Myeongwhan Hyun
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Patent number: 12147664Abstract: A system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a correlation component that, based on performance data, such as current performance data and/or historical performance data, for an application stored at a storage system, correlates a performance category with the application, and an execution component that, based on the performance category correlated to the application, executes a modification at the storage system, wherein the modification at the storage system comprises changing a functioning of the storage system relative to the application. In an embodiment, the data comprised by the application can be maintained in a non-accessed state to execute the modification at the storage system.Type: GrantFiled: December 23, 2022Date of Patent: November 19, 2024Assignee: NETAPP, INC.Inventors: Nathanael Black, Ashwin Palani, Jeffrey MacFarland
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Patent number: 12147525Abstract: The present disclosure relates to methods and systems for evaluating a storage medium. The method may include receiving, via a user interface of a host, a user request to evaluate a storage medium coupled to a first controller. The method may also include determining whether there is a first binding history table associated with the storage medium stored in the host. In response to a determination that there is no first binding history table stored in the host, the method may include retrieving a binding history table from the storage medium via the first controller and determining the storage medium as a second-hand storage medium if there is at least one second controller different from the first controller in the binding history table.Type: GrantFiled: April 25, 2023Date of Patent: November 19, 2024Assignee: INNOGRIT TECHNOLOGIES CO., LTD.Inventors: Moyang Chen, Zining Wu
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Patent number: 12147315Abstract: A system identifies an intent policy model associated with an initial time. The system updates a data structure to cause the data structure to include one or more portions. Each portion of the data structure is associated with a start time and an end time. Each portion includes: a first delta snapshot that indicates one or more first changes to the intent policy model from the initial time to the start time associated with the portion, and one or more additional delta snapshots that respectively indicate one or more incremental changes to the intent policy model at times from the start time and to the end time associated with the portion of the data structure.Type: GrantFiled: November 29, 2022Date of Patent: November 19, 2024Assignee: Juniper Networks, Inc.Inventors: Chandrasekhar A, Premchandar N, Jayanthi R
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Patent number: 12141069Abstract: A data processing apparatus is provided. Prefetch circuitry generates a prefetch request for a cache line prior to the cache line being explicitly requested. The cache line is predicted to be required for a store operation in the future. Issuing circuitry issues the prefetch request to a memory hierarchy and filter circuitry filters the prefetch request based on at least one other prefetch request made to the cache line, to control whether the prefetch request is issued by the issuing circuitry.Type: GrantFiled: December 28, 2022Date of Patent: November 12, 2024Assignee: Arm LimitedInventors: Luca Maroncelli, Cedric Denis Robert Airaud, Florent Begon, Peter Raphael Eid
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Patent number: 12112165Abstract: Systems, methods, and apparatus including computer-readable mediums for managing status information of logic units are provided. In one aspect, a device includes a semiconductor device including one or more logic units and a reporting bus and a controller coupled to the semiconductor device and configured to store status information of the one or more logic units in the semiconductor device. Each of the one or more logic units is configured to send information associated with the logic unit using a corresponding reporting unit in the semiconductor device through the reporting bus to the controller to indicate a status of the logic unit. The controller is configured to, in response to receiving the information associated with the logic unit, update corresponding status information of the logic unit based on the status of the logic unit.Type: GrantFiled: September 29, 2022Date of Patent: October 8, 2024Assignee: Macronix International Co., Ltd.Inventors: Sheng-Lun Wu, Chun-Lien Su
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Patent number: 12093143Abstract: A method for execution by a distributed storage network begins by receiving a request to transfer a copy of a set of encoded data slices from at least some associated virtual storage vaults to a destination virtual storage vault and continues by determining whether the destination storage unit supports a source virtual storage vault of the at least some source virtual storage vaults. When the destination storage unit supports the source virtual storage vault the method continues by determining a sub-set of encoded data slices of the set of encoded data slices for transfer and finally, by facilitating sending the sub-set of encoded data slices to the destination storage unit.Type: GrantFiled: March 10, 2023Date of Patent: September 17, 2024Assignee: Pure Storage, Inc.Inventors: Adam M. Gray, Greg R. Dhuse, Andrew D. Baptist, Ravi V. Khadiwala, Wesley B. Leggette, Scott M. Horan, Franco V. Borich, Bart R. Cilfone, Daniel J. Scholl
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Patent number: 12086473Abstract: Copying data using references to the data, including: receiving a request to write the source data to a target volume, wherein the request to write the source data indicates the reference information; obtaining a metadata representation of the source data using the reference information; an copying, using the reference information, the metadata representation of the source data to the target volume.Type: GrantFiled: April 20, 2023Date of Patent: September 10, 2024Assignee: PURE STORAGE, INC.Inventors: Roland Dreier, Rachel Shanava, Krishna Kant
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Patent number: 12086454Abstract: A data processing system includes an external memory system, a processor and an internal memory system. The internal memory system includes an internal memory that stores data for use by the processor when performing data processing operations. The internal memory system also includes a data encoder associated with the internal memory. The data encoder reads data from the external memory system to the data encoder and returns the data to the external memory system from the data encoder, without storing the data in the internal memory.Type: GrantFiled: November 18, 2021Date of Patent: September 10, 2024Assignee: Arm LimitedInventors: Olof Henrik Uhrenholt, Andreas Due Engh-Halstvedt
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Patent number: 12086467Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.Type: GrantFiled: February 28, 2023Date of Patent: September 10, 2024Assignee: Macronix International Co., Ltd.Inventors: Ting-Yu Liu, Yi-Chun Liu
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Patent number: 12079491Abstract: A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.Type: GrantFiled: January 5, 2023Date of Patent: September 3, 2024Assignees: Samsung Electronics Co., Ltd., Dongguk University Industry-Academic Cooperation FoundationInventors: Taewoo Han, Wooil Kim, Taehun Kim
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Patent number: 12073090Abstract: A system comprising a row hammer mitigation circuitry and a cache memory that collaborate to mitigate row hammer attacks on a memory media device is described. The cache memory biases cache policy based on row access count information maintained by the row hammer mitigation circuit. The row hammer mitigation circuitry may be implemented in a memory controller. The memory media device may be DRAM. Corresponding methods are also described.Type: GrantFiled: September 9, 2022Date of Patent: August 27, 2024Assignee: Micron Technology, Inc.Inventors: Edmund Gieske, Cagdas Dirik
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Patent number: 12050806Abstract: A distributed data storage system using erasure coding (EC) provides advantages of EC data storage while retaining high resiliency for EC data storage architectures having fewer data storage nodes than the number of EC data-plus-parity fragments. An illustrative embodiment is a three-node data storage system with EC 4+2. Incoming data is temporarily replicated to ameliorate the effects of certain storage node outages or fatal disk failures, so that read and write operations can continue from/to the storage system. The system is equipped to automatically heal failed EC write attempts in a manner transparent to users and/or applications: when all storage nodes are operational, the distributed data storage system automatically converts the temporarily replicated data to EC storage and reclaims storage space previously used by the temporarily replicated data. Individual hardware failures are healed through migration techniques that reconstruct and re-fragment data blocks according to the governing EC scheme.Type: GrantFiled: February 21, 2023Date of Patent: July 30, 2024Assignee: Commvault Systems, Inc.Inventors: Anand Vishwanath Vastrad, Avinash Lakshman, Suhani Gupta, Srinivas Lakshman
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Patent number: 12045142Abstract: A memory image can be captured by generating metadata indicative of a state of volatile memory and/or byte-addressable PMEM at a particular time during execution of a process by an application. This memory image can be persisted without copying the in-memory data into a separate persistent storage by storing the metadata and safekeeping the in-memory data in the volatile memory and/or PMEM. Metadata associated with multiple time-evolved memory images captured can be stored and managed using a linked index scheme. A linked index scheme can be configured in various ways including a full index and a difference-only index. The memory images can be used for various purposes including suspending and later resuming execution of the application process, restoring a failed application to a previous point in time, cloning an application, and recovering an application process to a most recent state in an application log.Type: GrantFiled: November 29, 2022Date of Patent: July 23, 2024Assignee: MEMVERGE, INC.Inventors: Ronald S. Niles, Yue Li, Jun Gan, Chenggong Fan, Robert W. Beauchamp
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Patent number: 12038835Abstract: An apparatus comprises a processing device configured to initiate garbage collection for data pages stored in local storage of a storage node of a storage system. The processing device is also configured to determine, for a given data page stored in the local storage of the storage node, a validity score characterizing a size of changed data in the given data page, and to compare the validity score for the given data page to at least one designated threshold. The processing device is further configured to update a given page object for the given data page in an object store of persistent storage responsive to a first comparison result, and to generate, in the object store of the persistent storage, a page delta object for the given data page responsive to a second comparison result, the page delta object comprising the changed data in the given data page.Type: GrantFiled: October 12, 2022Date of Patent: July 16, 2024Assignee: Dell Products L.P.Inventors: Doron Tal, Amitai Alkalay
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Patent number: 12039187Abstract: The present disclosure provides a power-down test method for a firmware of a memory system, a memory system, a computer device, a computer-readable storage medium, and a power-down test system. The disclosed method for testing power-down operations of the firmware of the memory system comprises configuring the firmware by setting a plurality of power-down trigger signal points each associated with a corresponding one of the plurality of preset logic points to be tested, and triggering a plurality of power-down test operations at the plurality of power-down trigger signal points to test the plurality of preset logic points of the firmware.Type: GrantFiled: August 8, 2022Date of Patent: July 16, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Yaofeng Jiang
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Patent number: 12026095Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.Type: GrantFiled: November 21, 2022Date of Patent: July 2, 2024Assignee: ARTERIS, INC.Inventors: David A. Kruckemyer, Craig Stephen Forrest
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Patent number: 12019549Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.Type: GrantFiled: January 12, 2022Date of Patent: June 25, 2024Assignee: Micron Technology, Inc.Inventors: Kenneth Marion Curewitz, Ameen D. Akel, Samuel E. Bradshaw, Sean Stephen Eilert, Dmitri Yudanov
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Patent number: 11995328Abstract: Implementations described herein relate to memory devices including a single-level cell (SLC) block storing data for migration to multiple multi-level cell (MLC) blocks. In some implementations, a memory device includes multiple MLC blocks that include MLCs, with each MLC being capable of storing at least four bits of data, and multiple SLC blocks that can store data prior to the data being written to one of the MLC blocks. Each SLC block may be capable of storing different data sets that are destined for storage in different MLC blocks. The memory device may include a mapping component that can store a mapping table that includes multiple entries, in which an entry indicates a mapping between a memory location in the SLC blocks and a corresponding MLC block for which data stored in the memory location is destined. Numerous other implementations are described.Type: GrantFiled: August 18, 2022Date of Patent: May 28, 2024Assignee: Micron Technology, Inc.Inventors: Johnny Au Lam, Nathaniel Wessel
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Patent number: 11995340Abstract: A read-disturb-based read temperature information access system includes a read-disturb-based read temperature information management subsystem coupled to a plurality of storage devices that each include a read-disturb-based read temperature information Application Programming Interface (API). Each storage device generates and stores read-disturb-based read temperature information associated with that storage device, and when a read-disturb-based read temperature information command is received from the read-disturb-based read temperature information management subsystem that conforms to the read-disturb-based read temperature information API, the storage device receiving that read-disturb-based read temperature information command will execute it to perform at least one operation using the read-disturb-based read temperature information associated with and stored by that storage device.Type: GrantFiled: January 19, 2022Date of Patent: May 28, 2024Assignee: Dell Products L.P.Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson, James Ulery