Patents Examined by Mark A Laurenzi, III
  • Patent number: 9683576
    Abstract: An impeller of a centrifugal compressor, the impeller including a web and blades secured to the web on a front face of the web. A point of intersection between a trailing edge and a blade root is at least one half-thickness of the web further forward than the blade root at an intermediate diameter of the impeller, and a point of intersection between the trailing edge and the blade tip is also further forward than the blade tip at an intermediate diameter of the impeller.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: June 20, 2017
    Assignee: TURBOMECA
    Inventors: Mathieu Herran, Laurent Pierre Tarnowski
  • Patent number: 9428373
    Abstract: A rotary-type filling machine includes a rotary body, a liquid distribution chamber, a plurality of filling flow path configuration units, each of which has a fluid path constituted by a liquid path connected to the liquid distribution chamber and a liquid valve and configured to individually introduce a liquid into a container, a filling control device, a liquid supply unit, a pressure difference information detection unit configured to detect pressure difference information between a liquid distribution chamber pressure, which is a pressure of the liquid in the liquid distribution chamber, and a filling atmospheric pressure detected as a pressure of a flow release unit in a filling flow path configuration unit at an arbitrary radial direction position of the rotary body, and a rotation information detection unit configured to detect rotation information of the rotary body.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: August 30, 2016
    Assignee: MITSUBISHI HEAVY INDUSTRIES FOOD & PACKAGING MACHINE CO., LTD.
    Inventors: Yoshiharu Tanaka, Masayuki Hayashi, Shinji Ishikura
  • Patent number: 9314085
    Abstract: A mascara application system includes an applicator for mascara and a mascara container. The applicator may include two brushes, and have a reverse tweezers arrangement, by which the brushes may be spaced apart from one another when pressure is applied to a handle portion of the applicator, and the brushes may be positioned adjacent to one another when no pressure is applied to the handle portion. An optional applicator container may hold a handle portion of the applicator, while enabling its actuation to operate the applicator. The mascara container, which holds mascara and is configured to receive the brushes, may include a separate portal for each brush, as well as a squeegee or other element for removing excess mascara from each brush. Methods for applying mascara to lashes are also disclosed.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 19, 2016
    Assignee: LASH DUET, LLC
    Inventor: Lisa Hatch
  • Patent number: 9266139
    Abstract: A paint/stain stick pad, for use with a paint/stain reservoir handle and dispensing plunger for coating deck boards with opposing side edges having joints therebetween, has a platform having a top and a bottom. The top has a pivotal connection to the handle and a paint/stain inlet in flow communication with the paint/stain in the reservoir handle. The bottom has a paint/stain dispensing and spreading surface in flow communication with the paint/stain inlet for evenly dispensing the paint/stain along the dispensing surface onto the boards. A central cut out is provided in the platform into which a stain/paint applicator is mounted in a floating arrangement within the cut out and biased downwardly as to dispense paint/stain onto the opposing board edges in the joints.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: February 23, 2016
    Assignee: Diversified Dynamics Corp.
    Inventors: Daniel Bruggeman, Dion McDevitt, Stephen Kohs
  • Patent number: 9254027
    Abstract: A device that is a packaged, individual deodorant powder applicator comprised of an application sheet with a non-impervious surface and a perimeter, an external sealed sheet surface, with a perimeter, the surface being impervious to liquids, capable of containing powder, and able to act as packaging; a means for sealing, at the perimeters, the external sheet surface to the application sheet, such as an adhesive; a powder reservoir created between the interior of the application sheet and the external sheet and contained by the sealed perimeter; powder within the reservoir; a means for closing the device halves without tab, such as adhesive; and a means for holding device such as a handle/spine wherein the sheets are configured and sealed to hold the powder in the reservoir where the using person may hold the device and apply the powder to the selected user's surface.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: February 9, 2016
    Inventor: Cathy Jo Emery
  • Patent number: 9202966
    Abstract: The present invention relates to a photovoltaic module structure 1 and to a method for establishing an electrically conductive connection between two spaced contact layers 4?, 6?, in particular in the photovoltaic module structure 1 according to the invention. The production method is particularly simple and economical and the photovoltaic module structure 1 according to the invention enables a significant gain in efficiency.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: December 1, 2015
    Assignee: Calyxo GmbH
    Inventors: Frank Becker, Michael Bauer, Jochen Frenck, Robert Fischer
  • Patent number: 9196532
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Yian-Liang Kuo, Wen-Hsiung Lu, Hsien-Wei Chen, Tsung-Fu Tsai
  • Patent number: 9138941
    Abstract: Provided is an example method of preparing a porous metal oxide structure, the method including adsorbing a metal oxide precursor onto a template having a networked structure of branched polynucleotides, decomposing and converting the adsorbed metal oxide precursor into a metal oxide, and removing the template. The networked structure of branched polynucleotides may be used as a template so as to facilitate control of the pore structure of a porous metal oxide structure.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: September 22, 2015
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Kyu-Hyun Im, No-kyoung Park, Jae-hyun Hur, Sang-Won Kim, Sung-jee Kim
  • Patent number: 9093404
    Abstract: The light-emitting device includes a first lower electrode, a second lower electrode, a partition, a layer with high conductivity, light-emitting layers, and an upper electrode. The conductivity of the layer with high conductivity is higher than the conductivity of each of the light-emitting layers and lower than the conductivity of each of the lower electrodes and the upper electrode. The partition includes a first slope located on a first lower electrode side and a second slope located on a second lower electrode side. The thickness of the layer with high conductivity located over the first slope in a direction perpendicular to the first slope is different from the thickness of the layer with high conductivity located over the second slope in a direction perpendicular to the second slope.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: July 28, 2015
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Kohei Yokoyama, Tomohiro Kosaka, Fumikazu Shimoshikiryoh, Shinichi Kawato, Katsuhiro Kikuchi, Manabu Niboshi, Takashi Ochi, Yuto Tsukamoto, Tomofumi Osaki
  • Patent number: 9006036
    Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoko Higashino, Yuichi Morinaga, Kazuya Tsuboi, Tamaki Wada
  • Patent number: 8803254
    Abstract: One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third metal layer comprised of titanium aluminum (TiAl) positioned above the second metal layer, a fourth metal layer comprised of an aluminum-containing material positioned above the third metal layer, a fifth metal layer comprised of titanium positioned above the fourth metal layer, and a layer of aluminum positioned above the fifth metal layer.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: August 12, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jean-Baptiste Laloe, Huang Liu, Wonwoo Kim
  • Patent number: 8766262
    Abstract: An organic light-emitting display device preventing edge defects between a pixel define layer and a pixel electrode, and a method of manufacturing the same. The organic light-emitting display device, comprises: a substrate; a pixel electrode disposed on the substrate and comprising a first patterned unit and a second patterned unit which are electrically disconnected; a pixel define unit disposed on the substrate and exposing the pixel electrode; an intermediate layer disposed on the pixel electrode and emitting light; and a counter electrode disposed on the intermediate layer and the pixel define layer.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Won Lee, Young-Il Kim, Seong-Ho Kim
  • Patent number: 8017999
    Abstract: An output side of a driver output circuit of an LCD driver includes a first protective element having an n-type semiconductor region and a p-type semiconductor region formed in the n-type semiconductor region, and a second protective element having a p-type semiconductor region and an n-type semiconductor region formed in the p-type semiconductor region. The first and second protective elements are arranged in twos, respectively, adjacent to each other.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 7998827
    Abstract: A method of manufacturing a semiconductor device, includes forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area, and aligning a third layer provided above the structure by using the second alignment mark.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaaki Hatano
  • Patent number: 7989800
    Abstract: A nanowire field effect junction diode constructed on an insulating transparent substrate that allows form(s) of radiation such as visual light, ultraviolet radiation; or infrared radiation to pass. A nanowire is disposed on the insulating transparent substrate. An anode is connected to a first end of the nanowire and a cathode is connected to the second end of the nanowire. An oxide layer covers the nanowire. A first conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the anode. A second conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the cathode and adjacent with a non-zero separation the first conducting gate. A controllable PN junction may be dynamically formed along the nanowire channel by applying opposite gate voltages. Radiation striking the nanowire through the substrate creates a current the anode and cathode.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: August 2, 2011
    Assignee: George Mason Intellectual Properties, Inc.
    Inventors: Qiliang Li, Dimitris E. Ioannou, Yang Yang, Xiaoxiao Zhu
  • Patent number: 7982281
    Abstract: According to one embodiment of the present invention, a SOI device includes a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer; a trench structure being formed within the first composite structure; and a second composite structure provided on the side walls of the trench structure, wherein the second composite structure includes a first isolation layer covering the part of the side walls formed by the semiconductor layer and formed by an upper part of the buried layer; and a contact layer covering the isolation layer and the part of the side walls formed by a lower part of the buried layer.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: July 19, 2011
    Assignee: Infineon Technologies AG
    Inventor: Gabriel Dehlinger
  • Patent number: 7964433
    Abstract: Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: June 21, 2011
    Assignee: California Institute of Technology
    Inventors: Youngsam Bae, Harish Manohara, Sohrab Mobasser, Choonsup Lee
  • Patent number: 7960758
    Abstract: A bipolar transistor and a radio frequency amplifier circuit capable of preventing thermal runaway in the bipolar transistor without affecting the radio frequency amplifier circuit, which includes: a direct-current (DC) bias terminal to which a DC bias is supplied; a DC base electrode connected to the DC terminal; a radio frequency (RF) power terminal to which a radio frequency signal is supplied; an RF base electrode connected to the RF terminal; and a base layer connected to the DC base electrode and the RF base electrode.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: June 14, 2011
    Assignee: Panasonic Corporation
    Inventor: Masahiro Maeda
  • Patent number: 7960715
    Abstract: Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantum dots experience negative hydrostatic pressure or high positive hydrostatic pressure, whereby a phase transitions may occur, and/or to create exciton crystals.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: June 14, 2011
    Assignee: University of Iowa Research Foundation
    Inventors: Craig Pryor, Mats-Erik Pistol
  • Patent number: 7960734
    Abstract: A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: June 14, 2011
    Assignees: STMicroelectronics (Crolles 2) SAS, Interuniversitair Micro-Electronica Centrum
    Inventor: Damien Lenoble