Abstract: A dynamic logic hold time latch (20). The latch comprises a first phase circuit (12?) operable in a precharge phase and an evaluate phase and a second phase circuit (22) operable in a precharge phase and an evaluate phase. The precharge phase and the evaluate phase of the second phase circuit are out of phase with respect to the precharge phase and the evaluate phase of the first phase circuit. The first phase circuit comprises a precharge node (12?PN) to be precharged to a precharge voltage during the precharge phase of the first phase circuit and operable to be discharged during the evaluate phase of the first phase circuit. The first phase circuit also comprises an output (12?OUT) for providing a signal in response to a state at the precharge node of the first phase circuit.