Abstract: A method for detecting word line shorts in a memory device includes: determining a region of interest (ROI) region in a bright voltage contrast (BVC) image for contact through-holes (CTs) of word lines in the memory device, the CTs comprising first CTs in at least one first word line that is electronically charged and second CTs in at least one second word line that is not electronically charged, and the ROI region comprising the at least one first word line; determining coordinates of each CT in the ROI region; reviewing a grayscale value at a position of the coordinates of each CT in the ROI region to determine whether the CT is a defective CT; and displaying the defective CT in response to the defective CT being determined.

Abstract: A cache coherency test process is provided which includes deterministically generating a test program to test cache coherency in a computing environment including at least one processing unit. The deterministically generating includes producing cache state test sequences using graph traversal, where the cache state test sequences include closed paths of cache-affecting operations, and where using graph traversal includes traversing one or more state graphs with nodes representing cache states and edges representing operations producing respective cache state transitions in the at least one processing unit. Further, the deterministically generating includes pruning the cache state test sequences, using closed-path graph analysis, to generate the test program, where the test program has a selected cache coherence test coverage using chosen cache state test sequences obtained from pruning the cache state test sequences.

Abstract: Supply chain security for chiplets is described. In accordance with the described techniques, a chiplet manufacturing interface obtains first test results, and stores an encrypted version of the first test results in a database accessible by the chiplet manufacturing interface and a chiplet integration interface. The chiplet integration interface obtains second test results from at least one chiplet, retrieves, from the database, the encrypted version of the first test results, decrypts the encrypted version of the first test results to obtain a first hash of the first test results, and selectively integrates the at least one chiplet into an integrated circuit based on a comparison of the first test results and the second test results and a comparison of the first hash and a second hash of the second test results generated by the chiplet integration interface.

Abstract: A method of a first terminal may comprise: transmitting first SCI to a second terminal and a third terminal; transmitting a first TB to the second terminal and the third terminal based on scheduling by the first SCI; receiving a HARQ feedback including NACK information for the first TB through a first PSFCH resource; determining whether NACK information for at least one terminal among the second terminal and the third terminal has been received, based on the HARQ feedback; and in response to determining that the NACK information has been received, retransmitting the first TB to the at least one terminal.

Abstract: An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S1, S2, and S3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

Abstract: A system and method are disclosed for decoding data from a memory device. For example, a controller can perform a read operation to receive the data. The controller executes a first decoding operation to correct a bit error in one or more weak bits of the data. In some instances, during the first decoding operation, one or more strong bits are skipped. The controller determines whether any bit errors remain in the data in response to the execution of the first decoding operation. The controller executes a second decoding operation to correct a bit error in one or more strong bits of the data and any remaining weak bits in the data that had not been corrected by the decoder during the first decoding operation in response to determining the data has errors. The controller outputs corrected data in response to correcting errors in the data.

Abstract: A learning control device according to one embodiment includes one or more hardware processors. The hardware processors function as an update unit, a calculation unit, and a correction unit. The update unit serves to update a modified control input in accordance with a tracking error. The modified control input is used during a learning trial. The calculation unit serves to calculate a lag in a learning control start time in accordance with a state of a control target at a start of the learning control. The learning control start time is a time at which learning control starts. The correction unit serves to correct the modified control input having been updated by the update unit. The modified control input is corrected by using the lag to have a value obtained by offsetting the lag.

Abstract: A method comprises receiving a request to predict a type and a quantity of respective ones of a plurality of resources for a computing environment. Using a multiple output classification and regression machine learning model, the type and the quantity of the respective ones of the plurality of resources are predicted in response to the request. The machine learning model is trained with a dataset comprising historical resource data corresponding to respective ones of a plurality of users.

Abstract: A method performed by a wireless transmit/receive unit (WTRU) may compromise: receiving configured grant (CG) information that includes: a configured grant period, an indication of a number of slots for Transport Block over Multiple Slots (TBoMS), and a mapping pattern; determining, for the CG period, a number of repetitions for a transport block (TB) based on (1) available UL slots in the CG period and (2) the number of slots for TBoMS; and on condition that DMRS bundling is disabled, and the determined number of repetitions is greater than 1, transmitting the TB with the determined number of repetitions where segments of the TB are transmitted according to the mapping pattern for each repetition.

Abstract: Aspects of the disclosure include sending inputs according to the Floquet codes to be processed by a quantum circuit and receiving data streams from the quantum circuit, in response to the inputs. The data streams are encoded into a predetermined number of bits according to a probability density function for noise. The data streams are classified into hard outcomes having likelihoods of correctness, the hard outcomes representing output of the quantum circuit.

Abstract: A communication system is a communication system that includes first and second information processing devices. The first information processing device performs control such that a signal (which is a signal having backward compatibility) serving as an index by which the second information processing device receiving a frame stops the reception of the frame is transmitted to the second information processing device. The second information processing device performs control such that the reception of the frame is stopped based on the signal (which is a signal having backward compatibility) serving as an index by which reception of the frame is stopped when the frame transmitted from the first information processing device is received.

Abstract: At least one processor may obtain a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus. The at least one processor may next generate a test data sequence including an interleaving of respective task procedures of the plurality of test pattern data sets, where the generating of the test data sequence includes generating sleep instructions for respective cores of the plurality of cores in accordance with the interleaving. The at least one processor may then apply the test data sequence via the shared testing input bus.

Abstract: This application discloses decoding methods, apparatuses, and computer-readable storage media, which may be applied to a plurality of scenarios such as a metropolitan area network, a backbone network, and data center interconnection. An example method includes: obtaining syndromes corresponding to a plurality of codewords; grouping the syndromes into groups; and sorting priorities of each group of syndromes; and selecting, based on a priority sorting result of each group of syndromes, a syndrome for decoding.

Abstract: A torn-write self-detection feature is implemented by a storage volume, which can be a single storage device or a plurality of storage devices. In one embodiment, page protection metadata is added to each data page. The metadata can include a data page size and a unique serial number for each group of sectors this data page is spanning. The page size and unique serial number can be stored in association with the data for each sector group. The unique serial number can follow a pattern, such as an incremental pattern. Upon a read of the data page, the page size and the unique serial number are checked for each sector group. If the serial numbers are consistent with the pattern, and the page size is correct, then the data is passed to the requesting host. Otherwise, a torn-write error condition is indicated to the host.

Abstract: Systems and methods provide reception of an identifier of a machine learning classification model and a prediction generated by the machine learning classification model, identification of model configuration data associated with the machine learning classification model, modification of the prediction based on the model configuration data to generate an enhanced prediction comprising calibrated probabilities, and returning of the enhanced prediction.

Abstract: There is provided a scan cell placing method including calculating a weight of each scan cell from a deterministic pattern input to a plurality of scan cells, dividing the scan cells into a coverage group and a power group on the basis of the weights, forming a plurality of power subgroups from a result of providing a pseudo random pattern to scan cells belonging to the power group, and scheduling one or more of the power subgroups to reduce peak power in a test process.

Abstract: A method of performing a reshape operation specified in a reshape layer of a neural network model is described. The reshape operation reshapes an input tensor with an input tensor shape to an output tensor with an output tensor shape. The tensor data that has to be reshaped is directly routed between tile memories of the hardware accelerator in an efficient manner. This advantageously optimizes usage of memory space and allows any number and type of neural network models to be run on the hardware accelerator.

Abstract: A circuit comprises: a plurality of identical circuit blocks, each of the plurality of identical circuit blocks comprising one or more test output ports; a first bit-combining device and a second bit-combining device for each of the one or more test output ports; a delay device for each of the one or more test output ports; and a network coupled to each of the plurality of identical circuit blocks and configured to transport a first bit stream and a second bit stream during a test, wherein the first bit-combining device and the second bit-combining device are configured to combine bits outputted from the each of the one or more test output ports with bits of the first bit stream and bits of the second bit stream that are delayed by the delay device, respectively.

Abstract: An apparatus is provided that includes a memory array and a control circuit. The memory array includes non-volatile memory cells each including a resistive random access memory element. The control circuit is configured to receive a read command that specifies an address of a first group of the non-volatile memory cells, use a first predetermined read reference value to perform a first read of the first group of the non-volatile memory cells to provide first read data, while performing the first read, retrieve from a memory a second predetermined read reference value corresponding to the specified address, and in response to a condition being satisfied regarding the first read data, use the second predetermined read reference value to perform a second read of the first group of the non-volatile memory cells to provide second read data.

Abstract: Methods, systems, and devices for host system diagnostic testing are described. A diagnostic tool including a diagnostic executable stored to an external memory may evaluate a system including a host subsystem and a memory subsystem. Upon initialization, the diagnostic executable may configure trace points in one or more layers (e.g., associated with an operating system) of the host subsystem based on dependencies (e.g., libraries) stored to the external memory, and may receive, from the host subsystem, first data collected at the trace points, directly from a host system buffer, or from the memory subsystem. Concurrent to the collection procedure, the diagnostic executable may perform processing operations on the first data to generate second data, which may be associated with one or more metrics of system performance. The second data is stored to the external memory, and may be utilized to evaluate the system.