Abstract: A low density parity check encoding method, including: determining a target parity check matrix, where the target parity check matrix belongs to a second parity check matrix set, and a base graph of the second parity check matrix set is extracted from a base graph of a first parity check matrix set and performing low density parity check encoding on data to be transmitted according to the target parity check matrix and a target lifting size.

Abstract: A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.

Abstract: Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.

Abstract: A memory device includes a mode register configured to store a first code for indicating termination resistance of the memory device and a second code for disabling a defective resistor, and an output driver including a plurality of pull-up units including a plurality of pull-up resistors and a plurality of pull-down units including a plurality of pull-down resistors. The output driver is configured to disable or enable respective pull-up resistors and pull-down resistors based on the second code, enable a subset of pull-up units from among the plurality of pull-up units including the respective pull-up resistors based on the first code, and enable a subset of pull-down unit from among the plurality of pull-down units including the respective pull-down resistors based on the first code.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to one of a plurality of word lines and disposed in memory holes coupled to bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the bit lines and for a group of the memory cells divided into a plurality of subsets, is configured to determine whether comparatively fewer read errors of the memory cells arise while pre-charging ones of the bit lines associated with each of the plurality of subsets. The control means is also configured to pre-charge ones of the bit lines associated with one the plurality of subsets with comparatively fewer read errors and read the memory cells associated therewith during a scan operation.

Abstract: A non-volatile memory is configured to perform multiple leak tests integrated into a pre-erase process for a set (e.g., block) of non-volatile memory cells after the set of non-volatile memory cells have received programming. An inference circuit is configured to use results of the leak tests with a pre-trained model to predict whether the set of non-volatile memory cells will fail.

Abstract: A method includes determining a plurality of threshold margins corresponding to a plurality of functional paths in an electronic circuit. The method further includes storing the plurality of threshold margins corresponding to the plurality of functional paths in a memory. The method further includes receiving a first trigger from a processing device. The method further includes responsive to receiving the first trigger, monitoring at least one of the plurality of threshold margins corresponding to at least one of the plurality of functional paths in view of a previously determined threshold margin stored in the memory and corresponding to the at least one of the plurality functional paths.

Abstract: An electronic circuit features a hybrid scan chain design comprising a flip-flop-based part of the scan chain and a latch-based part of the scan chain. The latch-based part may be included in an array of memory cells and includes one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The circuit includes a memory element interfacing the scan out (SO) output of the flip-flop-based scan chain with the scan in (SI) input of the latch-based scan chain. The memory element captures and retains the value of the final flip-flop in the flip-flop-based scan chain, enabling subsequent access by the initial latch in the latch-based scan chain without loss of data.

Abstract: An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.

Abstract: The methods and systems provide remote device recovery using a sideband communication path in response to an error occurring in the device. A management entity sends a sideband communication using the sideband communication path to a logic circuit in communication with the device. The logic circuit initiates the recovery of the device.

Abstract: Certain aspects of the disclosure provide a method for training a language model (LM) including: generating, using an LM, one or more outputs; computing a confidence score of an output of the one or more outputs based on a perplexity value of the output; determining, by a group relative policy optimization (GRPO)-based model, that the output is: associated with a correct status based on a reference policy; and associated with an uncertain status based on the confidence score and a threshold; determining, by the GRPO-based model, an increased reward value for the output that is associated with the correct status and the uncertain status based at least in part on a base reward value and the confidence score; causing, by the GRPO-based model, a reinforcement of the output using the increased reward value; and training the LM in accordance with the reinforcement of the output.

Abstract: According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

Abstract: A method for detecting word line shorts in a memory device includes: determining a region of interest (ROI) region in a bright voltage contrast (BVC) image for contact through-holes (CTs) of word lines in the memory device, the CTs comprising first CTs in at least one first word line that is electronically charged and second CTs in at least one second word line that is not electronically charged, and the ROI region comprising the at least one first word line; determining coordinates of each CT in the ROI region; reviewing a grayscale value at a position of the coordinates of each CT in the ROI region to determine whether the CT is a defective CT; and displaying the defective CT in response to the defective CT being determined.

Abstract: A cache coherency test process is provided which includes deterministically generating a test program to test cache coherency in a computing environment including at least one processing unit. The deterministically generating includes producing cache state test sequences using graph traversal, where the cache state test sequences include closed paths of cache-affecting operations, and where using graph traversal includes traversing one or more state graphs with nodes representing cache states and edges representing operations producing respective cache state transitions in the at least one processing unit. Further, the deterministically generating includes pruning the cache state test sequences, using closed-path graph analysis, to generate the test program, where the test program has a selected cache coherence test coverage using chosen cache state test sequences obtained from pruning the cache state test sequences.

Abstract: Supply chain security for chiplets is described. In accordance with the described techniques, a chiplet manufacturing interface obtains first test results, and stores an encrypted version of the first test results in a database accessible by the chiplet manufacturing interface and a chiplet integration interface. The chiplet integration interface obtains second test results from at least one chiplet, retrieves, from the database, the encrypted version of the first test results, decrypts the encrypted version of the first test results to obtain a first hash of the first test results, and selectively integrates the at least one chiplet into an integrated circuit based on a comparison of the first test results and the second test results and a comparison of the first hash and a second hash of the second test results generated by the chiplet integration interface.

Abstract: A method of a first terminal may comprise: transmitting first SCI to a second terminal and a third terminal; transmitting a first TB to the second terminal and the third terminal based on scheduling by the first SCI; receiving a HARQ feedback including NACK information for the first TB through a first PSFCH resource; determining whether NACK information for at least one terminal among the second terminal and the third terminal has been received, based on the HARQ feedback; and in response to determining that the NACK information has been received, retransmitting the first TB to the at least one terminal.

Abstract: An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S1, S2, and S3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

Abstract: A system and method are disclosed for decoding data from a memory device. For example, a controller can perform a read operation to receive the data. The controller executes a first decoding operation to correct a bit error in one or more weak bits of the data. In some instances, during the first decoding operation, one or more strong bits are skipped. The controller determines whether any bit errors remain in the data in response to the execution of the first decoding operation. The controller executes a second decoding operation to correct a bit error in one or more strong bits of the data and any remaining weak bits in the data that had not been corrected by the decoder during the first decoding operation in response to determining the data has errors. The controller outputs corrected data in response to correcting errors in the data.

Abstract: A learning control device according to one embodiment includes one or more hardware processors. The hardware processors function as an update unit, a calculation unit, and a correction unit. The update unit serves to update a modified control input in accordance with a tracking error. The modified control input is used during a learning trial. The calculation unit serves to calculate a lag in a learning control start time in accordance with a state of a control target at a start of the learning control. The learning control start time is a time at which learning control starts. The correction unit serves to correct the modified control input having been updated by the update unit. The modified control input is corrected by using the lag to have a value obtained by offsetting the lag.

Abstract: A method comprises receiving a request to predict a type and a quantity of respective ones of a plurality of resources for a computing environment. Using a multiple output classification and regression machine learning model, the type and the quantity of the respective ones of the plurality of resources are predicted in response to the request. The machine learning model is trained with a dataset comprising historical resource data corresponding to respective ones of a plurality of users.