Abstract: The signal separation device includes a memory. The memory includes a test circuit, a first buffer, and a command terminal. The test circuit is configured to output a test signal. The first buffer is configured to output a first delay signal according to the test signal. The command terminal is configured to output a command path signal according to the test signal and the first delay signal. The first buffer is coupled between the test circuit and the command terminal.

Abstract: A method for generating a low-density parity-check code, including: arranging t block matrices along a diagonal to form a local matrix, wherein the t block matrices are identical and do not overlap; the block matrix has m rows and n columns; interposing an all-zero matrix between each two adjacent columns of the block matrix to separate the n columns and form an expanded global matrix, wherein each all-zero matrix has a size of m×(t?1); permutating the expanded global matrix rightward circularly in sequence to generate t expanded global matrices, and arranging the t expanded global matrices under the local matrix in sequence to form a basic parity-check matrix. The present invention can flexibly adjust the code length and the CPM size of the basic parity-check matrix, reducing the complexity of the parity-check matrix to further simplify the implementation of the decoder hardware.

Abstract: The technology disclosed herein includes a memory to store a plurality of pages, a page of the plurality of pages configured as one of a trusted execution environment (TEE) configuration and a non-TEE configuration, and a memory controller to attempt to access the page using a memory address and the TEE configuration and generate a first error correcting code (ECC); and when data for the first ECC is at least one of correct and correctable by ECC for the attempt to access the page using the TEE configuration, attempt to access the page using the memory address and the non-TEE configuration and generate a second ECC, and when data the second ECC is at least one of correct and correctable by ECC for the attempt to access the page using the non-TEE configuration, store the memory address as an unknown cacheline address.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a receiver. The receiver receives, from a transmitter, a signal carrying a constellation symbol. The receiver processes the received signal by a soft symbol demapper to generate a first soft output of a first set of bits and a second soft output of a second set of bits. The receiver processes the second soft output by a soft syndrome former to generate a third soft output of a third set of bits. The soft syndrome former corresponds to a shaping code applied at the transmitter. The receiver recovers bits represented by the constellation symbol based on the first soft output and the third soft output.

Abstract: A method for generating perspective(s) of a knowledge graph includes receiving the knowledge graph from a database, wherein the knowledge graph includes vertices at least partially connected together by edges; generating a property graph of the knowledge graph, including vertices at least partially connected together by edges; creating metagraph transformation(s) to be executed on the property graph for generating perspective(s) of the knowledge graph, wherein each metagraph transformation is lazily evaluated on the property graph; validating at least one metagraph transformation based on the lazy evaluation of on the property graph against a set of user-defined schema configurations; detecting a set of errors in the at least one metagraph transformation, if the at least one metagraph transformation is not successfully validated against the set of user-defined schema configurations; and displaying the set of errors to a user for adjusting the at least one metagraph transformation

Abstract: A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data.

Abstract: In an example, a first testing device is configured to receive testing data from a second testing. The first testing device is configured to send a stimulus to a device under test. The first testing device obtains test data reception methods and test data reception formats that are compatible with the first testing device and translates the methods and formats into content that is readable by the second testing device. The content is received by the second testing device, which accesses test data transmission methods and formats compatible with the second testing device and defines an intersection of the reception and transmission test data formats. The second testing device sends the intersection of methods and formats to the first testing device, which reduces the intersection to a final method and format.

Abstract: A method of operating a device in a wireless network comprising transmitting a first uplink signal comprising control information in a set of uplink resources, transmitting a second uplink signal, wherein the second uplink signal is to be transmitted a plurality of times, each of the plurality of transmissions of the second uplink signal being a repetition of the second uplink signal, wherein each repetition of the second uplink signal is to be transmitted in a different set of uplink resources to the other repetitions of the second uplink signal, determining that the resources of the first uplink signal at least partially overlap in time with the resources of at least one of the repetitions of the second uplink signal, multiplexing the control information into the resources of a selected one or more of the repetitions of the second uplink signal, and transmitting the multiplexed signal to the wireless network.

Abstract: Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.

Abstract: A circuit for detecting an error in a byte of data transmitted over a channel includes a controller having a first DBI encoder configured to perform a first DBI encoding on a received byte of data. The circuit also includes a channel configured to receive the encoded byte from the controller. The circuit also includes a non-volatile memory having a second DBI encoder and configured to (1) perform a second DBI encoding on the encoded byte received over the channel, (2) check a DBI flag for the byte after the second DBI encoding, and (3) determine that the byte of data contains an error when the DBI flag after the second DBI encoding is 1. If the byte contains an error then it can be concluded that the channel contains a defect. In case of an error a write operation to memory core can be stopped.

Abstract: A processing apparatus for a neural network calculation and an operating method thereof are proposed. The processing apparatus for a neural network calculation according to an exemplary embodiment includes a plurality of processor units which performs the learning of a neural network, a plurality of weight memories provided to store a weight corresponding to each of a plurality of layers which forms the neural network, and a main memory which acquires and stores the weight updated from the plurality of weight memories when the learning is completed.

Abstract: A low density parity check encoding method, including: determining a target parity check matrix, where the target parity check matrix belongs to a second parity check matrix set, and a base graph of the second parity check matrix set is extracted from a base graph of a first parity check matrix set and performing low density parity check encoding on data to be transmitted according to the target parity check matrix and a target lifting size.

Abstract: A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.

Abstract: Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.

Abstract: A memory device includes a mode register configured to store a first code for indicating termination resistance of the memory device and a second code for disabling a defective resistor, and an output driver including a plurality of pull-up units including a plurality of pull-up resistors and a plurality of pull-down units including a plurality of pull-down resistors. The output driver is configured to disable or enable respective pull-up resistors and pull-down resistors based on the second code, enable a subset of pull-up units from among the plurality of pull-up units including the respective pull-up resistors based on the first code, and enable a subset of pull-down unit from among the plurality of pull-down units including the respective pull-down resistors based on the first code.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to one of a plurality of word lines and disposed in memory holes coupled to bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the bit lines and for a group of the memory cells divided into a plurality of subsets, is configured to determine whether comparatively fewer read errors of the memory cells arise while pre-charging ones of the bit lines associated with each of the plurality of subsets. The control means is also configured to pre-charge ones of the bit lines associated with one the plurality of subsets with comparatively fewer read errors and read the memory cells associated therewith during a scan operation.

Abstract: A method includes determining a plurality of threshold margins corresponding to a plurality of functional paths in an electronic circuit. The method further includes storing the plurality of threshold margins corresponding to the plurality of functional paths in a memory. The method further includes receiving a first trigger from a processing device. The method further includes responsive to receiving the first trigger, monitoring at least one of the plurality of threshold margins corresponding to at least one of the plurality of functional paths in view of a previously determined threshold margin stored in the memory and corresponding to the at least one of the plurality functional paths.

Abstract: A non-volatile memory is configured to perform multiple leak tests integrated into a pre-erase process for a set (e.g., block) of non-volatile memory cells after the set of non-volatile memory cells have received programming. An inference circuit is configured to use results of the leak tests with a pre-trained model to predict whether the set of non-volatile memory cells will fail.

Abstract: An electronic circuit features a hybrid scan chain design comprising a flip-flop-based part of the scan chain and a latch-based part of the scan chain. The latch-based part may be included in an array of memory cells and includes one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The circuit includes a memory element interfacing the scan out (SO) output of the flip-flop-based scan chain with the scan in (SI) input of the latch-based scan chain. The memory element captures and retains the value of the final flip-flop in the flip-flop-based scan chain, enabling subsequent access by the initial latch in the latch-based scan chain without loss of data.

Abstract: An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.