Abstract: An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments.A function-request facility provides a functional capability over certain objects within the GDP address space.

Abstract: A signal encoder and classifier particularly adapted to speech recognition includes a circularly addressed buffer which is independently addressed by a new data writing address system and a buffered data reading system so that writing and reading of data may be accomplished on a time shared basis. This time shared operation permits serial writing and reading of the pattern data without interrupting income signal storage. The writing data address system addresses the data into the buffer in a circular fashion while the reading data address system utilizes stored addresses identifying the beginning and end of the signal patterns for addressing sequential patterns from the buffer.

Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the task servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.